Patent | Date |
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Gate structures for transistor devices for CMOS applications and products Grant 9,362,283 - Hong , et al. June 7, 2 | 2016-06-07 |
Combinatorial screening of metallic diffusion barriers Grant 9,297,775 - Adhiprakasha , et al. March 29, 2 | 2016-03-29 |
Combinatorial screening of metallic diffusion barriers App 20150338362 - Adhiprakasha; Edwin ;   et al. | 2015-11-26 |
Methods Of Forming Gate Structures For Transistor Devices For Cmos Applications And The Resulting Products App 20150311206 - Hong; Zhendong ;   et al. | 2015-10-29 |
Methods of forming gate structures for transistor devices for CMOS applications Grant 9,105,497 - Hong , et al. August 11, 2 | 2015-08-11 |
Pillar devices and methods of making thereof Grant 8,987,119 - Dunton , et al. March 24, 2 | 2015-03-24 |
Methods Of Forming Gate Structures For Transistor Devices For Cmos Applications And The Resulting Products App 20150061027 - Hong; Zhendong ;   et al. | 2015-03-05 |
Process to remove Ni and Pt residues for NiPtSi application using chlorine gas Grant 8,859,431 - Duong , et al. October 14, 2 | 2014-10-14 |
Circular transmission line methods compatible with combinatorial processing of semiconductors Grant 8,854,067 - Joshi , et al. October 7, 2 | 2014-10-07 |
Patterning of submicron pillars in a memory array Grant 8,759,176 - Raghuram , et al. June 24, 2 | 2014-06-24 |
High productivity combinatorial oxide terracing and PVD/ALD metal deposition combined with lithography for gate work function extraction Grant 8,735,302 - Joshi , et al. May 27, 2 | 2014-05-27 |
Methods for protecting patterned features during trench etch Grant 8,722,518 - Radigan , et al. May 13, 2 | 2014-05-13 |
Circular Transmission Line Methods Compatible With Combinatorial Processing Of Semiconductors App 20140055152 - Joshi; Amol ;   et al. | 2014-02-27 |
High Productivity Combinatorial Oxide Terracing And Pvd/ald Metal Deposition Combined With Lithography For Gate Work Function Extraction App 20130316472 - Joshi; Amol ;   et al. | 2013-11-28 |
Process to remove Ni and Pt residues for NiPtSi application using Chlorine gas App 20130267091 - Duong; Anh ;   et al. | 2013-10-10 |
Methods For Protecting Patterned Features During Trench Etch App 20130244395 - Radigan; Steven J. ;   et al. | 2013-09-19 |
Process to remove Ni and Pt residues for NiPtSi applications using chlorine gas Grant 8,466,058 - Duong , et al. June 18, 2 | 2013-06-18 |
PROCESS TO REMOVE Ni AND Pt RESIDUES FOR NiPtSi APPLICATIONS USING CHLORINE GAS App 20130122670 - Duong; Anh ;   et al. | 2013-05-16 |
Dual damascene with amorphous carbon for 3D deep via/trench application Grant 8,298,931 - Raghuram , et al. October 30, 2 | 2012-10-30 |
Diode array and method of making thereof Grant 8,268,678 - Maxwell , et al. September 18, 2 | 2012-09-18 |
Spectroscopy And Spectral Imaging Methods And Apparatus App 20120200852 - Tejada; Francisco ;   et al. | 2012-08-09 |
Method of making a nonvolatile phase change memory cell having a reduced contact area Grant 8,163,593 - Raghuram , et al. April 24, 2 | 2012-04-24 |
Spectroscopy And Spectral Imaging Methods And Apparatus App 20120091550 - Morgan; Ricky James ;   et al. | 2012-04-19 |
Modified DARC stack for resist patterning Grant 8,084,366 - Chan , et al. December 27, 2 | 2011-12-27 |
Method For Reducing Dielectric Overetch Using A Dielectric Etch Stop At A Planar Surface App 20110306177 - Dunton; Samuel V. ;   et al. | 2011-12-15 |
Liner for tungsten/silicon dioxide interface in memory Grant 8,071,475 - Tanaka , et al. December 6, 2 | 2011-12-06 |
Method for reducing dielectric overetch using a dielectric etch stop at a planar surface Grant 8,008,187 - Dunton , et al. August 30, 2 | 2011-08-30 |
Pillar Devices And Methods Of Making Thereof App 20110136326 - DUNTON; Vance ;   et al. | 2011-06-09 |
Method of plasma etching transition metal oxides Grant 7,955,515 - Raghuram , et al. June 7, 2 | 2011-06-07 |
Method for forming doped polysilicon via connecting polysilicon layers Grant 7,915,163 - Konevecki , et al. March 29, 2 | 2011-03-29 |
Method for forming doped polysilicon via connecting polysilicon layers Grant 7,915,164 - Konevecki , et al. March 29, 2 | 2011-03-29 |
Diode Array and Method of Making Thereof App 20110065243 - Maxwell; Steven ;   et al. | 2011-03-17 |
Pillar devices and methods of making thereof Grant 7,906,392 - Dunton , et al. March 15, 2 | 2011-03-15 |
Method For Forming Doped Polysilicon Via Connecting Polysilicon Layers App 20110021019 - Konevecki; Michael W. ;   et al. | 2011-01-27 |
Diode array and method of making thereof Grant 7,846,782 - Maxwell , et al. December 7, 2 | 2010-12-07 |
Method For Reducing Dielectric Overetch Using A Dielectric Etch Stop At A Planar Surface App 20100297834 - Dunton; Samuel V. ;   et al. | 2010-11-25 |
Method for reducing dielectric overetch using a dielectric etch stop at a planar surface Grant 7,790,607 - Dunton , et al. September 7, 2 | 2010-09-07 |
Nonvolatile phase change memory cell having a reduced contact area Grant 7,728,318 - Raghuram , et al. June 1, 2 | 2010-06-01 |
Conductive Hard Mask To Protect Patterned Features During Trench Etch App 20090273022 - Radigan; Steven J. ;   et al. | 2009-11-05 |
Modified darc stack for resist patterning App 20090258495 - Chan; Michael ;   et al. | 2009-10-15 |
Method For Forming Doped Polysilicon Via Connecting Polysilicon Layers App 20090258462 - Konevecki; Michael W. ;   et al. | 2009-10-15 |
Patterning Of Submicron Pillars In A Memory Array App 20090224244 - Raghuram; Usha ;   et al. | 2009-09-10 |
Conductive hard mask to protect patterned features during trench etch Grant 7,575,984 - Radigan , et al. August 18, 2 | 2009-08-18 |
Doped polysilicon via connecting polysilicon layers Grant 7,566,974 - Konevecki , et al. July 28, 2 | 2009-07-28 |
Pillar devices and methods of making thereof App 20090179310 - Dunton; Vance ;   et al. | 2009-07-16 |
Method for patterning submicron pillars Grant 7,517,796 - Raghuram , et al. April 14, 2 | 2009-04-14 |
Liner For Tungsten/silicon Dioxide Interface In Memory App 20090085087 - Tanaka; Yoichiro ;   et al. | 2009-04-02 |
Diode Array And Method Of Making Thereof App 20090085153 - Maxwell; Steven ;   et al. | 2009-04-02 |
Dual Damascene With Amorphous Carbon For 3d Deep Via/trench Application App 20090087979 - Raghuram; Usha ;   et al. | 2009-04-02 |
Method for reducing dielectric overetch using a dielectric etch stop at a planar surface App 20080254615 - Dunton; Samuel V. ;   et al. | 2008-10-16 |
Method for reducing dielectric overetch using a dielectric etch stop at a planar surface Grant 7,422,985 - Dunton , et al. September 9, 2 | 2008-09-09 |
Nonvolatile Phase Change Memory Cell Having A Reduced Contact Area App 20080116441 - Raghuram; Usha ;   et al. | 2008-05-22 |
Method Of Making A Nonvolatile Phase Change Memory Cell Having A Reduced Contact Area App 20080119007 - Raghuram; Usha ;   et al. | 2008-05-22 |
Conductive hard mask to protect patterned features during trench etch App 20070284656 - Radigan; Steven J. ;   et al. | 2007-12-13 |
Nonselective unpatterned etchback to expose buried patterned features Grant 7,307,013 - Raghuram , et al. December 11, 2 | 2007-12-11 |
Method of plasma etching transition metals and their compounds App 20070010100 - Raghuram; Usha ;   et al. | 2007-01-11 |
Method for reducing dielectric overetch using a dielectric etch stop at a planar surface App 20060216937 - Dunton; Samuel V. ;   et al. | 2006-09-28 |
Method for patterning submicron pillars App 20060183282 - Raghuram; Usha ;   et al. | 2006-08-17 |
Doped polysilicon via connecting polysilicon layers App 20060071074 - Konevecki; Michael W. ;   et al. | 2006-04-06 |
Nonselective unpatterned etchback to expose buried patterned features App 20060003586 - Raghuram; Usha ;   et al. | 2006-01-05 |
Method for etching and/or patterning a silicon-containing layer Grant 6,890,860 - Wang , et al. May 10, 2 | 2005-05-10 |
Method of forming contact openings Grant 6,756,315 - Bamnolker , et al. June 29, 2 | 2004-06-29 |
Plasma etching method Grant 6,406,640 - Yang , et al. June 18, 2 | 2002-06-18 |