| Patent | Date |
|---|
Self-timed processors implemented with multi-rail null convention logic and unate gates
Grant 10,951,212 - Xu , et al. March 16, 2 | 2021-03-16 |
Self-timed clocked processor architecture
Grant 10,732,700 - Murtagh , et al. | 2020-08-04 |
Real time clock with neural network correction of temperature-based changes in frequency
Grant 10,666,268 - Raghavan | 2020-05-26 |
Real Time Clock With Neural Network Correction Of Temperature-based Changes In Frequency
App 20200052704 - Raghavan; Gopal | 2020-02-13 |
Neural Network For Continuous Speech Segmentation And Recognition
App 20190325862 - Shankar; Hari ; et al. | 2019-10-24 |
Self-timed Clocked Processor Architecture
App 20190196564 - Murtagh; Paul ; et al. | 2019-06-27 |
Self-timed Processors Implemented With Multi-rail Null Convention Logic And Unate Gates
App 20190190520 - Xu; Chao ; et al. | 2019-06-20 |
Asynchronous processor
Grant 10,248,187 - Raghavan | 2019-04-02 |
Self-timed processors implemented with multi-rail null convention logic and unate gates
Grant 10,205,453 - Xu , et al. Feb | 2019-02-12 |
Self-timed Processors Implemented With Multi-rail Null Convention Logic And Unate Gates
App 20180294810 - Xu; Chao ; et al. | 2018-10-11 |
Asynchronous Processor
App 20160328011 - Raghavan; Gopal | 2016-11-10 |
Asynchronous processor that adjusts a respective operating voltage for causing a task to consume substantially all of a respective allocated time interval for the task
Grant 9,423,866 - Raghavan August 23, 2 | 2016-08-23 |
Asynchronous Processor
App 20160018869 - Raghavan; Gopal | 2016-01-21 |
Memory Module And Memory System Having The Same
App 20140355327 - BYUN; Hyun Il ; et al. | 2014-12-04 |
Redriven/retimed registered dual inline memory module
Grant 8,898,368 - Haywood , et al. November 25, 2 | 2014-11-25 |
Load reduction system and method for DIMM-based memory systems
Grant 8,275,936 - Haywood , et al. September 25, 2 | 2012-09-25 |
Redriven/Retimed Registered Dual Inline Memory Module
App 20090119451 - Haywood; Christopher ; et al. | 2009-05-07 |
Output buffer with switchable output impedance
Grant 7,479,799 - Raghavan , et al. January 20, 2 | 2009-01-20 |
Master-slave flip-flop and clocking scheme
Grant 7,408,393 - Jain , et al. August 5, 2 | 2008-08-05 |
Programmable strength output buffer for RDIMM address register
Grant 7,307,863 - Yen , et al. December 11, 2 | 2007-12-11 |
Output buffer with switchable output impedance
App 20070216445 - Raghavan; Gopal ; et al. | 2007-09-20 |
Programmable strength output buffer for RDIMM address register
App 20070030752 - Yen; Jeffrey C. ; et al. | 2007-02-08 |
Output buffer with time varying source impedance for driving capacitively-terminated transmission lines
Grant 6,980,021 - Srivastava , et al. December 27, 2 | 2005-12-27 |
Output Buffer With Time Varying Source Impedance For Driving Capacitively-terminated Transmission Lines
App 20050280435 - Srivastava, Nikhil K. ; et al. | 2005-12-22 |
Symmetric planar inductor
App 20050077992 - Raghavan, Gopal ; et al. | 2005-04-14 |
Bipolar transistor-based linearizer with programmable gain and phase response system
Grant 6,750,709 - Raghavan , et al. June 15, 2 | 2004-06-15 |
Variable negative resistance cell for bipolar integrated circuits
Grant 6,621,331 - Pobanz , et al. September 16, 2 | 2003-09-16 |
Bipolar transistor-based linearizer with programmable gain and phase response system
App 20030102911 - Raghavan, Gopal ; et al. | 2003-06-05 |
Variable negative resistance cell for bipolar integrated circuits
App 20030030485 - Pobanz, Carl W. ; et al. | 2003-02-13 |
Flexible and programmable delta-sigma analog signal converter
Grant 5,952,947 - Nussbaum , et al. September 14, 1 | 1999-09-14 |
Positive current source
Grant 5,812,020 - Raghavan , et al. September 22, 1 | 1998-09-22 |
Differential nonlinear transmission line circuit
Grant 5,789,994 - Case , et al. August 4, 1 | 1998-08-04 |
Method of frabricating a MOS transistor having a composite gate electrode
Grant 5,783,478 - Chau , et al. July 21, 1 | 1998-07-21 |
Delta-Sigma .DELTA.-.SIGMA. modulator having a dynamically tunable continuous time Gm-C architecture
Grant 5,729,230 - Jensen , et al. March 17, 1 | 1998-03-17 |
NPN bipolar circuit topology for a tunable transconductance cell and positive current source
Grant 5,726,600 - Raghavan , et al. March 10, 1 | 1998-03-10 |
MOS transistor having a composite gate electrode and method of fabrication
Grant 5,625,217 - Chau , et al. April 29, 1 | 1997-04-29 |
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