loadpatents
name:-0.0048549175262451
name:-0.0047261714935303
name:-0.00062799453735352
Radzimski; Zbigniew J. Patent Filings

Radzimski; Zbigniew J.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Radzimski; Zbigniew J..The latest application filed is for "high resistivity silicon wafer with thick epitaxial layer and method of producing same".

Company Profile
0.4.9
  • Radzimski; Zbigniew J. - Brush Prairie WA
  • Radzimski, Zbigniew J. - Brush Prairrie WA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
High resistivity silicon wafer having electrically inactive dopant and method of producing same
Grant 6,673,147 - Kononchuk , et al. January 6, 2
2004-01-06
High resistivity silicon wafer produced by a controlled pull rate czochralski method
Grant 6,669,775 - Kononchuk , et al. December 30, 2
2003-12-30
Method of producing a high resistivity silicon wafer utilizing heat treatment that occurs during device fabrication
Grant 6,669,777 - Kononchuk , et al. December 30, 2
2003-12-30
Optimized silicon wafer gettering for advanced semiconductor devices
Grant 6,632,277 - Dietze , et al. October 14, 2
2003-10-14
High resistivity silicon wafer having electrically inactive dopant and method of producing same
App 20030106482 - Kononchuk, Oleg V. ;   et al.
2003-06-12
Method of producing a high resistivity silicon wafer utilizing heat treatment that occurs during device fabrication
App 20030106486 - Kononchuk, Oleg V. ;   et al.
2003-06-12
High Resistivity Silicon Wafer And Method Of Producing Same Using The Magnetic Field Czochralski Method
App 20030106485 - Kononchuk, Oleg V. ;   et al.
2003-06-12
High Resistivity Silicon Wafer With Thick Epitaxial Layer And Method Of Producing Same
App 20030109115 - Kononchuk, Oleg V. ;   et al.
2003-06-12
High resistivity silicon wafer produced by a controlled pull rate czochralski method
App 20030106481 - Kononchuk, Oleg V. ;   et al.
2003-06-12
Optimized silicon wafer strength for advanced semiconductor devices
App 20020020340 - Dietze, Gerald R. ;   et al.
2002-02-21
Optimized silicon wafer gettering for advanced semiconductor devices
App 20010015168 - Dietze, Gerald R. ;   et al.
2001-08-23
High efficiency silicon wafer optimized for advanced semiconductor devices
App 20010007240 - Dietze, Gerald R. ;   et al.
2001-07-12
Improved purity silicon wafer for use in advanced semiconductor devices
App 20010007241 - Dietze, Gerald R. ;   et al.
2001-07-12

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed