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Patent applications and USPTO patent grants for Radosevich; Joseph R..The latest application filed is for "formation of silicon on insulator (soi) devices as add-on modules for system on a chip processing".
Patent | Date |
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Formation of silicon on insulator (SOI) devices as add-on modules for system on a chip processing Grant 6,602,758 - Kizilyalli , et al. August 5, 2 | 2003-08-05 |
Formation of silicon on insulator (SOI) devices as add-on modules for system on a chip processing App 20020192956 - Kizilyalli, Isik C. ;   et al. | 2002-12-19 |
CMOS device fabrication utilizing selective laser anneal to form raised source/drain areas App 20020192914 - Kizilyalli, Isik C. ;   et al. | 2002-12-19 |
Metal silicide as a barrier for MOM capacitors in CMOS technologies Grant 6,335,557 - Kizilyalli , et al. January 1, 2 | 2002-01-01 |
Method for making a metal to metal capacitor Grant 5,576,240 - Radosevich , et al. November 19, 1 | 1996-11-19 |
Forming a device dielectric on a deposited semiconductor having sub-layers Grant 5,298,436 - Radosevich , et al. March 29, 1 | 1994-03-29 |
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