Radojcic; Ratibor

Patent Applications and Registrations

Patent applications and USPTO patent grants for Radojcic; Ratibor.The latest application filed is for "integrated circuit (ic) package comprising electrostatic discharge (esd) protection".

Company Profile

1.17.17

Radojcic; Ratibor - San Diego CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Bottom package with metal post interconnections Grant 10,971,476 - Gu , et al. April 6, 2	2021-04-06
Substrate block for PoP package Grant 9,881,859 - We , et al. January 30, 2	2018-01-30
Through-silicon via (TSV) crack sensors for detecting TSV cracks in three-dimensional (3D) integrated circuits (ICs) (3DICs), and related methods and systems Grant 9,869,713 - Lim , et al. January 16, 2	2018-01-16
Integrated circuit (IC) package comprising electrostatic discharge (ESD) protection Grant 9,853,446 - Gu , et al. December 26, 2	2017-12-26
Integrated device comprising a capacitor that includes multiple pins and at least one pin that traverses a plate of the capacitor Grant 9,704,796 - Gu , et al. July 11, 2	2017-07-11
Integrated device comprising flexible connector between integrated circuit (IC) packages Grant 9,633,977 - We , et al. April 25, 2	2017-04-25
Integrated Circuit (ic) Package Comprising Electrostatic Discharge (esd) Protection App 20170063079 - Gu; Shiqun ; et al.	2017-03-02
Anchoring Conductive Material In Semiconductor Devices App 20170005160 - GU; Shiqun ; et al.	2017-01-05
THROUGH-SILICON VIA (TSV) CRACK SENSORS FOR DETECTING TSV CRACKS IN THREE-DIMENSIONAL (3D) INTEGRATED CIRCUITS (ICs) (3DICs), AND RELATED METHODS AND SYSTEMS App 20160258996 - Lim; Sung Kyu ; et al.	2016-09-08
Integrated device comprising high density interconnects in inorganic layers and redistribution layers in organic layers Grant 9,418,877 - Gu , et al. August 16, 2	2016-08-16
Semiconductor Package With Incorporated Inductance Element App 20160133614 - GU; Shiqun ; et al.	2016-05-12
Method and apparatus for characterizing thermal marginality in an integrated circuit Grant 9,285,418 - Chakraborty , et al. March 15, 2	2016-03-15
SUBSTRATE BLOCK FOR PoP PACKAGE App 20150325509 - We; Hong Bok ; et al.	2015-11-12
Integrated Device Comprising High Density Interconnects In Inorganic Layers And Redistribution Layers In Organic Layers App 20150318262 - Gu; Shiqun ; et al.	2015-11-05
Enhanced package thermal management using external and internal capacitive thermal material Grant 9,136,202 - Chiriac , et al. September 15, 2	2015-09-15
Bottom Package With Metal Post Interconnections App 20150235991 - Gu; Shiqun ; et al.	2015-08-20
Integrated Device Comprising A Substrate With Aligning Trench And/or Cooling Cavity App 20150214127 - Gu; Shiqun ; et al.	2015-07-30
Low Cost Interposer Comprising An Oxidation Layer App 20140306349 - Gu; Shiqun ; et al.	2014-10-16
Dual Substrate, Power Distribution And Thermal Solution For Direct Stacked Integrated Devices App 20140225246 - Henderson; Brian Matthew ; et al.	2014-08-14
Hybrid package construction with wire bond and through silicon vias Grant 8,803,305 - Radojcic , et al. August 12, 2	2014-08-12
Voltage switchable dielectric for die-level electrostatic discharge (ESD) protection Grant 8,691,707 - Gu , et al. April 8, 2	2014-04-08
Voltage switchable dielectric for die-level electrostatic discharge (ESD) protection Grant 8,633,562 - Gu , et al. January 21, 2	2014-01-21
Voltage Switchable Dielectric For Die-level Electrostatic Discharge (esd) Protection App 20130316526 - Gu; Shiqun ; et al.	2013-11-28
Enhanced Package Thermal Management Using External And Internal Capacitive Thermal Material App 20130270721 - Chiriac; Victor A. ; et al.	2013-10-17
Voltage Switchable Dielectric for Die-Level Electrostatic Discharge (ESD) Protection App 20120248582 - Gu; Shiqun ; et al.	2012-10-04
Variable feature interface that induces a balanced stress to prevent thin die warpage Grant 8,076,762 - Chandrasekaran , et al. December 13, 2	2011-12-13
Hybrid Package Construction With Wire Bond And Through Silicon Vias App 20110115064 - Radojcic; Ratibor ; et al.	2011-05-19
Variable Feature Interface That Induces A Balanced Stress To Prevent Thin Die Warpage App 20110037156 - Chandrasekaran; Arvind ; et al.	2011-02-17
Designing an integrated circuit to improve yield using a variant design element Grant 7,487,474 - Ciplickas , et al. February 3, 2	2009-02-03
Yield improvement App 20060101355 - Ciplickas; Dennis ; et al.	2006-05-11

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