Radecker; Jorg

Patent Applications and Registrations

Patent applications and USPTO patent grants for Radecker; Jorg.The latest application filed is for "methods of recessing an active region and sti structures in a common etch process".

Company Profile

0.9.14

Radecker; Jorg - Dresden N/A DE

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Methods of recessing an active region and STI structures in a common etch process Grant 8,853,051 - Jakubowski , et al. October 7, 2	2014-10-07
Methods for fabricating semiconductor devices with isolation regions having uniform stepheights Grant 8,679,940 - Jakubowski , et al. March 25, 2	2014-03-25
Methods of forming isolation structures for semiconductor devices Grant 8,642,419 - Kronholz , et al. February 4, 2	2014-02-04
Methods Of Recessing An Active Region And Sti Structures In A Common Etch Process App 20130273709 - Jakubowski; Frank ; et al.	2013-10-17
Methods Of Forming Isolation Structures For Semiconductor Devices By Employing A Spin-on Glass Material Or A Flowable Oxide Material App 20130221478 - Kronholz; Stephan ; et al.	2013-08-29
Methods Of Forming Isolation Structures For Semiconductor Devices App 20130214381 - Kronholz; Stephan ; et al.	2013-08-22
Methods For Fabricating Semiconductor Devices With Isolation Regions Having Uniform Stepheights App 20130217205 - Jakubowski; Frank ; et al.	2013-08-22
Methods Of Forming Stepped Isolation Structures For Semiconductor Devices Using A Spacer Technique App 20130214392 - Kronholz; Stephan ; et al.	2013-08-22
Method for manufacturing an integrated circuit including a transistor Grant 7,718,475 - Goldbach , et al. May 18, 2	2010-05-18
Method for manufacturing a transistor App 20080251815 - Goldbach; Matthias ; et al.	2008-10-16
Integrated circuit formed on a semiconductor substrate App 20070105302 - Birner; Albert ; et al.	2007-05-10
Method for fabricating a self-aligning mask Grant 7,125,778 - Efferenn , et al. October 24, 2	2006-10-24
Method for fabricating a semiconductor structure with an encapsulation of a filling which is used for filling trenches Grant 6,908,831 - O'Riain , et al. June 21, 2	2005-06-21
Method For Fabricating A Semiconductor Structure With An Encapsulation Of A Filling Which Is Used For Filling Trenches App 20050095788 - O'Riain, Lincoln ; et al.	2005-05-05
Method for fabricating a self-aligning mask App 20030040184 - Efferenn, Dirk ; et al.	2003-02-27

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.