loadpatents
name:-0.018494129180908
name:-0.022897005081177
name:-0.0045549869537354
Quay; Stephen Thomas Patent Filings

Quay; Stephen Thomas

Patent Applications and Registrations

Patent applications and USPTO patent grants for Quay; Stephen Thomas.The latest application filed is for "automatic layer trait generation and promotion cost computation".

Company Profile
3.18.11
  • Quay; Stephen Thomas - Vancouver CA
  • Quay; Stephen Thomas - Austin TX
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Automatic Layer Trait Generation And Promotion Cost Computation
App 20200380082 - Quay; Stephen Thomas ;   et al.
2020-12-03
Automatic layer trait generation and promotion cost computation
Grant 10,839,122 - Quay , et al. November 17, 2
2020-11-17
Net layer promotion with swap capability in electronic design
Grant 10,831,971 - Quay , et al. November 10, 2
2020-11-10
Timing driven routing in integrated circuit design
Grant 8,386,985 - Alpert , et al. February 26, 2
2013-02-26
Timing Driven Routing In Integrated Circuit Design
App 20120284683 - Alpert; Charles Jay ;   et al.
2012-11-08
Techniques for super fast buffer insertion
Grant 7,676,780 - Alpert , et al. March 9, 2
2010-03-09
Techniques for super fast buffer insertion
Grant 7,392,493 - Alpert , et al. June 24, 2
2008-06-24
Techniques For Super Fast Buffer Insertion
App 20080072202 - Alpert; Charles Jay ;   et al.
2008-03-20
Probabilistic congestion prediction with partial blockages
Grant 7,299,442 - Alpert , et al. November 20, 2
2007-11-20
Method and apparatus for performing density-biased buffer insertion in an integrated circuit design
Grant 7,137,081 - Alpert , et al. November 14, 2
2006-11-14
Method and apparatus for generating steiner trees using simultaneous blockage avoidance, delay optimization and design density management
Grant 7,127,696 - Alpert , et al. October 24, 2
2006-10-24
Probabilistic congestion prediction with partial blockages
App 20060156266 - Alpert; Charles Jay ;   et al.
2006-07-13
Porosity aware buffered steiner tree construction
Grant 7,065,730 - Alpert , et al. June 20, 2
2006-06-20
Techniqes for super fast buffer insertion
App 20060112364 - Alpert; Charles Jay ;   et al.
2006-05-25
Apparatus and method for incorporating driver sizing into buffer insertion using a delay penalty estimation technique
Grant 6,915,496 - Alpert , et al. July 5, 2
2005-07-05
Method and apparatus for generating steiner trees using simultaneous blockage avoidance, delay optimization and design density management
App 20050138578 - Alpert, Charles Jay ;   et al.
2005-06-23
Method and apparatus for performing density-biased buffer insertion in an integrated circuit design
App 20050138589 - Alpert, Charles Jay ;   et al.
2005-06-23
Buffer insertion with adaptive blockage avoidance
Grant 6,898,774 - Alpert , et al. May 24, 2
2005-05-24
Porosity aware buffered steiner tree construction
App 20040216072 - Alpert, Charles Jay ;   et al.
2004-10-28
Buffer insertion with adaptive blockage avoidance
App 20040123261 - Alpert, Charles Jay ;   et al.
2004-06-24
Apparatus and method for incorporating driver sizing into buffer insertion using a delay penalty estimation technique
App 20040064793 - Alpert, Charles Jay ;   et al.
2004-04-01
Apparatus and method for determining buffered steiner trees for complex circuits
Grant 6,591,411 - Alpert , et al. July 8, 2
2003-07-08
Apparatus and method for buffer library selection for use in buffer insertion
Grant 6,560,752 - Alpert , et al. May 6, 2
2003-05-06
Apparatus and method for determining buffered steiner trees for complex circuits
App 20020133799 - Alpert, Charles Jay ;   et al.
2002-09-19
Method and system for re-routing interconnects within an integrated circuit design having blockages and bays
Grant 6,401,234 - Alpert , et al. June 4, 2
2002-06-04
Method and apparatus for performing buffer insertion with accurate gate and interconnect delay computation
Grant 6,347,393 - Alpert , et al. February 12, 2
2002-02-12
Optimum buffer placement for noise avoidance
Grant 6,117,182 - Alpert , et al. September 12, 2
2000-09-12
Method and system for segmenting wires prior to buffer insertion
Grant 6,044,209 - Alpert , et al. March 28, 2
2000-03-28

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