Quan; Gabriel

Patent Applications and Registrations

Patent applications and USPTO patent grants for Quan; Gabriel.The latest application filed is for "method and apparatus for performing fast incremental physical design optimization".

Company Profile

2.19.3

Quan; Gabriel - Toronto CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method and apparatus for performing fast incremental physical design optimization Grant 11,093,672 - Khan , et al. August 17, 2	2021-08-17
Method And Apparatus For Performing Fast Incremental Physical Design Optimization App 20200257839 - A1	2020-08-13
Method and apparatus for performing fast incremental physical design optimization Grant 10,635,772 - Khan , et al.	2020-04-28
Method and Apparatus for Implementing Soft Constraints in Tools Used for Designing Programmable Logic Devices App 20170337318 - Borer; Terry ; et al.	2017-11-23
Method and apparatus for implementing soft constraints in tools used for designing programmable logic devices Grant 9,754,065 - Borer , et al. September 5, 2	2017-09-05
Method and apparatus for performing fast incremental physical design optimization Grant 9,569,574 - Khan , et al. February 14, 2	2017-02-14
Method and Apparatus for Implementing Soft Constraints in Tools Used for Designing Programmable Logic Devices App 20140047405 - Borer; Terry ; et al.	2014-02-13
M/A for performing incremental compilation using top-down and bottom-up design approaches Grant 8,589,838 - Borer , et al. November 19, 2	2013-11-19
Method and apparatus for implementing soft constraints in tools used for designing programmable logic devices Grant 8,589,849 - Borer , et al. November 19, 2	2013-11-19
Specifying placement and routing constraints for security and redundancy Grant 8,434,044 - Goldman , et al. April 30, 2	2013-04-30
Method and apparatus for performing incremental compilation using top-down and bottom-up design approaches Grant 8,250,505 - Borer , et al. August 21, 2	2012-08-21
Method and apparatus for performing incremental compilation using top-down and bottom-up design approaches Grant 7,669,157 - Borer , et al. February 23, 2	2010-02-23
Method and apparatus for performing layout-driven optimizations on field programmable gate arrays Grant 7,594,204 - Singh , et al. September 22, 2	2009-09-22
Method and apparatus for performing incremental compilation Grant 7,464,362 - Borer , et al. December 9, 2	2008-12-09
Method and apparatus for performing retiming on field programmable gate arrays Grant 7,360,190 - Singh , et al. April 15, 2	2008-04-15
Method and apparatus for performing logic replication in field programmable gate arrays Grant 7,257,800 - Singh , et al. August 14, 2	2007-08-14
Method and apparatus for implementing soft constraints in tools used for designing systems on programmable logic devices Grant 7,194,720 - Borer , et al. March 20, 2	2007-03-20
Method and apparatus for placement of components onto programmable logic devices Grant 7,181,717 - Singh , et al. February 20, 2	2007-02-20
Method and apparatus for placement of components onto programmable logic devices Grant 6,779,169 - Singh , et al. August 17, 2	2004-08-17

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