Puvvada; Venugopal
Patent Applications and Registrations
Patent applications and USPTO patent grants for Puvvada; Venugopal.The latest application filed is for "reducing time to design integrated circuits including performing electro-migration check".
- Puvvada; Venugopal - Bangalore IN
| Patent | Date |
|---|---|
| Timing closure for system on a chip using voltage drop based standard delay formats Grant 7,324,914 - Jain , et al. January 29, 2 | 2008-01-29 |
| Electro-migration (EM) and voltage (IR) drop analysis of integrated circuit (IC) designs Grant 7,315,992 - Bhooshan , et al. January 1, 2 | 2008-01-01 |
| Reducing Time To Design Integrated Circuits Including Performing Electro-migration Check App 20070079264 - Goda; Ananth Somayaji ; et al. | 2007-04-05 |
| Reducing time to design integrated circuits including performing electro-migration check Grant 7,197,730 - Goda , et al. March 27, 2 | 2007-03-27 |
| Timing closure for system on a chip using voltage drop based standard delay formats App 20060106564 - Jain; Atul K. ; et al. | 2006-05-18 |
| Electro-migration (EM) and Voltage (IR) Drop Analysis of Integrated Circuit (IC) Designs App 20060026540 - BHOOSHAN; Rishi ; et al. | 2006-02-02 |
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