Puri; Ruchir

Patent Applications and Registrations

Patent applications and USPTO patent grants for Puri; Ruchir.The latest application filed is for "system, method, and recording medium for mirroring matrices for batched cholesky decomposition on a graphic processing unit".

Company Profile

10.73.74

Puri; Ruchir - Baldwin Place NY
Puri; Ruchir - Yorktown Heights NY
Puri; Ruchir - Bladwin Place NY
Puri; Ruchir - Peekskill NY
Puri; Ruchir - New Rochelle NY
Puri; Ruchir - Danbury CT
Puri; Ruchir - Calgary CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
System, Method, And Recording Medium For Mirroring Matrices For Batched Cholesky Decomposition On A Graphic Processing Unit App 20210263994 - Cho; Minsik ; et al.	2021-08-26
Automatic correction of indirect bias in machine learning models Grant 11,068,797 - Bhide , et al. July 20, 2	2021-07-20
System, method, and recording medium for mirroring matrices for batched Cholesky decomposition on a graphic processing unit Grant 11,036,829 - Cho , et al. June 15, 2	2021-06-15
Building of Custom Convolution Filter for a Neural Network Using an Automated Evolutionary Process App 20210174175 - Choudhury; Mihir ; et al.	2021-06-10
Concept analysis operations utilizing accelerators Grant 10,963,794 - Acar , et al. March 30, 2	2021-03-30
Parallelized in-place radix sorting Grant 10,831,738 - Bordawekar , et al. November 10, 2	2020-11-10
System, method and computer program product for accelerating iterative graph algorithms by memory layout optimization Grant 10,740,232 - Cho , et al. A	2020-08-11
Model Agnostic Contrastive Explanations For Structured Data App 20200193243 - Dhurandhar; Amit ; et al.	2020-06-18
Radix sort acceleration using custom asic Grant 10,685,002 - Bordawekar , et al.	2020-06-16
Post-hoc Improvement Of Instance-level And Group-level Prediction Metrics App 20200184350 - Bhide; Manish ; et al.	2020-06-11
Parallel quicksort Grant 10,671,611 - Brand , et al.	2020-06-02
Automatic Correction Of Indirect Bias In Machine Learning Models App 20200134493 - Bhide; Manish ; et al.	2020-04-30
System, Method, and recording medium for mirroring matrices for batched Cholesky decomposition on a graphic processing unit Grant 10,572,569 - Cho , et al. Feb	2020-02-25
System, Method, And Recording Medium For Mirroring Matrices For Batched Cholesky Decomposition On A Graphic Processing Unit App 20200057790 - Cho; Minsik ; et al.	2020-02-20
Concept Analysis Operations Utilizing Accelerators App 20190354878 - Acar; Emrah ; et al.	2019-11-21
System, Method, And Recording Medium For Mirroring Matrices For Batched Cholesky Decomposition On A Graphic Processing Unit App 20190294651 - Cho; Minsik ; et al.	2019-09-26
System, method, and recording medium for mirroring matrices for batched Cholesky decomposition on a graphic processing unit Grant 10,423,695 - Cho , et al. Sept	2019-09-24
Concept analysis operations utilizing accelerators Grant 10,373,057 - Acar , et al.	2019-08-06
Matrix ordering for cache efficiency in performing large sparse matrix operations Grant 10,310,812 - Acar , et al.	2019-06-04
System, Method And Computer Program Product For Accelerating Iterative Graph Algorithms By Memory Layout Optimization App 20190114260 - Cho; Minsik ; et al.	2019-04-18
System, method and computer program product for accelerating iterative graph algorithms by memory layout optimization Grant 10,209,913 - Cho , et al. Feb	2019-02-19
Parallel Quicksort App 20180357283 - Brand; Daniel ; et al.	2018-12-13
Parallel quicksort Grant 10,108,670 - Brand , et al. October 23, 2	2018-10-23
System, Method And Computer Program Product For Accelerating Iterative Graph Algorithms By Memory Layout Optimization App 20180217775 - Cho; Minsik ; et al.	2018-08-02
Transformation on input operands to reduce hardware overhead for implementing addition Grant 10,037,190 - Choudhury , et al. July 31, 2	2018-07-31
System, Method, And Recording Medium For Mirroring Matrices For Batched Cholesky Decomposition On A Graphic Processing Unit App 20180196779 - Cho; Minsik ; et al.	2018-07-12
System, method, and recording medium for mirroring matrices for batched cholesky decomposition on a graphic processing unit Grant 9,984,041 - Cho , et al. May 29, 2	2018-05-29
Radix Sort Acceleration Using Custom Asic App 20180144010 - BORDAWEKAR; Rajesh ; et al.	2018-05-24
Parallelized In-place Radix Sorting App 20180121481 - BORDAWEKAR; Rajesh ; et al.	2018-05-03
Radix sort acceleration using custom ASIC Grant 9,953,044 - Bordawekar , et al. April 24, 2	2018-04-24
Adaptive radix external in-place radix sort Grant 9,946,512 - Cho , et al. April 17, 2	2018-04-17
Radix sort acceleration using custom ASIC Grant 9,928,261 - Bordawekar , et al. March 27, 2	2018-03-27
Parallelized in-place radix sorting Grant 9,892,149 - Bordawekar , et al. February 13, 2	2018-02-13
System, Method, And Recording Medium For Mirroring Matrices For Batched Cholesky Decomposition On A Graphic Processing Unit App 20180004707 - Cho; Minsik ; et al.	2018-01-04
Parallelized in-place radix sorting Grant 9,858,040 - Bordawekar , et al. January 2, 2	2018-01-02
Lookup table sharing for memory-based computing Grant 9,851,743 - Cho , et al. December 26, 2	2017-12-26
Mapping a lookup table to prefabricated TCAMS Grant 9,824,756 - Brand , et al. November 21, 2	2017-11-21
Parallelized in-place radix sorting Grant 9,824,111 - Bordawekar , et al. November 21, 2	2017-11-21
Parallelized in-place radix sorting Grant 9,823,896 - Bordawekar , et al. November 21, 2	2017-11-21
Transformation on Input Operands to Reduce Hardware Overhead for Implementing Addition App 20170277515 - Choudhury; Mihir ; et al.	2017-09-28
Lookup table sharing for memory-based computing Grant 9,760,110 - Cho , et al. September 12, 2	2017-09-12
Matrix Ordering for Cache Efficiency in Performing Large Sparse Matrix Operations App 20170147287 - Acar; Emrah ; et al.	2017-05-25
Adaptive Radix External In-place Radix Sort App 20170090817 - CHO; Minsik ; et al.	2017-03-30
Matrix ordering for cache efficiency in performing large sparse matrix operations Grant 9,606,934 - Acar , et al. March 28, 2	2017-03-28
Parallel Quicksort App 20170053000 - Brand; Daniel ; et al.	2017-02-23
Concept Analysis Operations Utilizing Accelerators App 20160299975 - Acar; Emrah ; et al.	2016-10-13
Matrix Ordering for Cache Efficiency in Performing Large Sparse Matrix Operations App 20160224473 - Acar; Emrah ; et al.	2016-08-04
Lookup Table Sharing For Memory-based Computing App 20160161976 - CHO; Minsik ; et al.	2016-06-09
Lookup Table Sharing For Memory-based Computing App 20160154767 - CHO; MINSIK ; et al.	2016-06-02
Lookup table sharing for memory-based computing Grant 9,304,972 - Cho , et al. April 5, 2	2016-04-05
Lookup table sharing for memory-based computing Grant 9,304,971 - Cho , et al. April 5, 2	2016-04-05
Parallelized In-place Radix Sorting App 20150302038 - BORDAWEKAR; Rajesh ; et al.	2015-10-22
Parallelized In-place Radix Sorting App 20150301799 - BORDAWEKAR; Rajesh ; et al.	2015-10-22
Radix Sort Acceleration Using Custom Asic App 20150293957 - BORDAWEKAR; Rajesh ; et al.	2015-10-15
Radix Sort Acceleration Using Custom Asic App 20150212797 - BORDAWEKAR; Rajesh ; et al.	2015-07-30
Parallelized In-place Radix Sorting App 20150213076 - BORDAWEKAR; Rajesh ; et al.	2015-07-30
Parallelized In-place Radix Sorting App 20150213114 - BORDAWEKAR; Rajesh ; et al.	2015-07-30
Mapping A Lookup Table To Prefabricated Tcams App 20150052298 - Brand; Daniel ; et al.	2015-02-19
Lookup Table Sharing For Memory-based Computing App 20150006600 - CHO; MINSIK ; et al.	2015-01-01
Lookup Table Sharing For Memory-based Computing App 20150006599 - CHO; MINSIK ; et al.	2015-01-01
Specifying circuit level connectivity during circuit design synthesis Grant 8,839,162 - Amundson , et al. September 16, 2	2014-09-16
Relative ordering circuit synthesis Grant 8,756,541 - Cho , et al. June 17, 2	2014-06-17
Automated synthesis of high-performance two operand binary parallel prefix adder Grant 8,683,398 - Choudhury , et al. March 25, 2	2014-03-25
Automated critical area allocation in a physical synthesized hierarchical design Grant 8,656,332 - Fleischer , et al. February 18, 2	2014-02-18
Structured Latch and Local-Clock-Buffer Planning App 20130326451 - Cho; Minsik ; et al.	2013-12-05
Network flow based datapath bit slicing Grant 8,566,761 - Xiang , et al. October 22, 2	2013-10-22
Relative Ordering Circuit Synthesis App 20130263068 - Cho; Minsik ; et al.	2013-10-03
Automated synthesis of high-performance two operand binary parallel prefix adder Grant 8,527,920 - Choudhury , et al. September 3, 2	2013-09-03
Soft hierarchy-based physical synthesis for large-scale, high-performance circuits Grant 8,516,412 - Cho , et al. August 20, 2	2013-08-20
Structured latch and local-clock-buffer planning Grant 8,495,552 - Cho , et al. July 23, 2	2013-07-23
Network Flow Based Datapath Bit Slicing App 20130132915 - Cho; Minsik ; et al.	2013-05-23
Soft Hierarchy-based Physical Synthesis For Large-scale, High-performance Circuits App 20130055176 - Cho; Minsik ; et al.	2013-02-28
Logic modification synthesis Grant 8,365,114 - Arbel , et al. January 29, 2	2013-01-29
Converged large block and structured synthesis for high performance microprocessor designs Grant 8,271,920 - Cho , et al. September 18, 2	2012-09-18
Network flow based module bottom surface metal pin assignment Grant 8,261,226 - Becker , et al. September 4, 2	2012-09-04
Converged Large Block And Structured Synthesis For High Performance Microprocessor Designs App 20120054699 - Cho; Minsik ; et al.	2012-03-01
Logic Modification Synthesis App 20120054698 - Arbel; Eli ; et al.	2012-03-01
Logic difference synthesis Grant 8,122,400 - Hopkins , et al. February 21, 2	2012-02-21
Apparatus, method and computer program product for fast simulation of manufacturing effects during integrated circuit design Grant 8,117,568 - Xiang , et al. February 14, 2	2012-02-14
Regular local clock buffer placement and latch clustering by iterative optimization Grant 8,104,014 - Puri , et al. January 24, 2	2012-01-24
Specifying Circuit Level Connectivity During Circuit Design Synthesis App 20120017186 - Amundson; Michael D. ; et al.	2012-01-19
Three-dimensional cascaded power distribution in a semiconductor device Grant 8,053,819 - Bernstein , et al. November 8, 2	2011-11-08
Method and apparatus for parallel processing of semiconductor chip designs Grant 8,020,134 - Dotson , et al. September 13, 2	2011-09-13
Clock power minimization with regular physical placement of clock repeater components Grant 8,010,926 - Alpert , et al. August 30, 2	2011-08-30
Stage mitigation of interconnect variability Grant 7,930,669 - Lavin , et al. April 19, 2	2011-04-19
Wafer level I/O test, repair and/or customization enabled by I/O layer Grant 7,913,202 - Bernstein , et al. March 22, 2	2011-03-22
Logic Difference Synthesis App 20110004857 - Hopkins; Jeremy T. ; et al.	2011-01-06
Automated Critical Area Allocation in a Physical Synthesized Hierarchical Design App 20100218155 - Fleischer; Bruce M. ; et al.	2010-08-26
Apparatus, Method and Computer Program Product for Fast Stimulation of Manufacturing Effects During Integrated Circuit Design App 20100077372 - Xiang; Hua ; et al.	2010-03-25
System and method for global circuit routing incorporating estimation of critical area estimate metrics Grant 7,685,553 - Papadopoulou , et al. March 23, 2	2010-03-23
Logic block timing estimation using conesize Grant 7,676,779 - Bergamaschi , et al. March 9, 2	2010-03-09
Method And Apparatus For Parallel Processing Of Semiconductor Chip Designs App 20090217227 - DOTSON; MICHAEL W. ; et al.	2009-08-27
Clock Power Minimization With Regular Physical Placement Of Clock Repeater Components App 20090193376 - Alpert; Charles J. ; et al.	2009-07-30
Regular Local Clock Buffer Placement And Latch Clustering By Iterative Optimization App 20090193377 - Puri; Ruchir ; et al.	2009-07-30
Integrated circuit (IC) chip design method, program product and system Grant 7,552,412 - Abbaspour , et al. June 23, 2	2009-06-23
Wafer level I/O test and repair enabled by I/O layer Grant 7,521,950 - Bernstein , et al. April 21, 2	2009-04-21
Logic Block Timing Estimation Using Conesize App 20090070719 - Bergamaschi; Reinaldo A. ; et al.	2009-03-12
System to Identify Timing Differences from Logic Block Changes and Associated Methods App 20090070720 - Bergamaschi; Reinaldo A. ; et al.	2009-03-12
Influence-based circuit design Grant 7,500,207 - Bhattacharya , et al. March 3, 2	2009-03-03
Multiple Voltage Integrated Circuit And Design Method Therefor App 20090032903 - Correale, JR.; Anthony ; et al.	2009-02-05
Multiple voltage integrated circuit and design method therefor Grant 7,480,883 - Correale, Jr. , et al. January 20, 2	2009-01-20
Stage Mitigation Of Interconnect Variability App 20090019415 - Lavin; Mark A. ; et al.	2009-01-15
Integrated Circuit (ic) Design Method And Method Of Analyzing Radiation-induced Single-event Upsets In Cmos Logic Designs App 20080281572 - Puri; Ruchir ; et al.	2008-11-13
Design stage mitigation of interconnect variability Grant 7,448,014 - Lavin , et al. November 4, 2	2008-11-04
System And Method For Global Circuit Routing Incorporating Estimation Of Critical Area Estimate Metrics App 20080256502 - Papadopoulou; Evanthia ; et al.	2008-10-16
Three-Dimensional Cascaded Power Distribution in a Semiconductor Device App 20080203445 - Bernstein; Kerry ; et al.	2008-08-28
Three-dimensional cascaded power distribution in a semiconductor device Grant 7,402,854 - Bernstein , et al. July 22, 2	2008-07-22
Three-dimensional Architecture For Self-checking And Self-repairing Integrated Circuits App 20080165521 - BERNSTEIN; KERRY ; et al.	2008-07-10
Wafer Level I/O Test, Repair and/or Customization Enabled by I/O layer App 20080068039 - Bernstein; Kerry ; et al.	2008-03-20
Single supply level converter Grant 7,336,100 - Correale, Jr. , et al. February 26, 2	2008-02-26
Three-dimensional cascaded power distribution in a semiconductor device App 20080023731 - Bernstein; Kerry ; et al.	2008-01-31
Cell placement in circuit design App 20070234259 - Drumm; Anthony D. ; et al.	2007-10-04
Design stage mitigation of interconnect variability App 20070214446 - Lavin; Mark A. ; et al.	2007-09-13
Influence-based circuit design App 20070192752 - Bhattacharya; Subhrajit ; et al.	2007-08-16
Clock tree distribution generation by determining allowed placement regions for clocked elements Grant 7,225,421 - Migatz , et al. May 29, 2	2007-05-29
Wafer Level I/o Test And Repair Enabled By I/o Layer App 20070081410 - Bernstein; Kerry ; et al.	2007-04-12
Multiple Voltage Integrated Circuit And Design Method Therefor App 20070028193 - Correale; Anthony JR. ; et al.	2007-02-01
Single Supply Level Converter App 20060279334 - Correale; Anthony JR. ; et al.	2006-12-14
Single supply level converter Grant 7,119,578 - Correale, Jr. , et al. October 10, 2	2006-10-10
Multiple voltage integrated circuit and design method therefor Grant 7,111,266 - Correale, Jr. , et al. September 19, 2	2006-09-19
Method Of Clock Tree Distribution Generation By Determining Allowed Placement Regions For Clocked Elements App 20060190899 - Migatz; William R. ; et al.	2006-08-24
Method and program product of level converter optimization Grant 7,089,510 - Correale, Jr. , et al. August 8, 2	2006-08-08
Integrated circuit (IC) chip design method, program product and system App 20060150133 - Abbaspour; Soroush ; et al.	2006-07-06
CMOS tapered gate and synthesis method Grant 6,966,046 - Curran , et al. November 15, 2	2005-11-15
Method for reducing wiring congestion in a VLSI chip design Grant 6,958,545 - Kotecha , et al. October 25, 2	2005-10-25
Method for reducing wiring congestion in a VLSI chip design App 20050151258 - Kotecha, Pooja M. ; et al.	2005-07-14
Single supply level converter App 20050110519 - Correale, Anthony JR. ; et al.	2005-05-26
Method and program product of level converter optimization App 20050114815 - Correale, Anthony JR. ; et al.	2005-05-26
Multiple voltage integrated circuit and design method therefor App 20050114814 - Correale, Anthony JR. ; et al.	2005-05-26
Logic circuit for true and complement signal generator Grant 6,724,225 - Joshi , et al. April 20, 2	2004-04-20
System and method for fast interconnect delay estimation through iterative refinement Grant 6,601,223 - Puri , et al. July 29, 2	2003-07-29
Logic or circuit App 20030006803 - Joshi, Rajiv V. ; et al.	2003-01-09
Logic circuit for true and complement signal generator App 20020186050 - Joshi, Rajiv V. ; et al.	2002-12-12
CMOS tapered gate and synthesis method App 20020157079 - Curran, Brian W. ; et al.	2002-10-24
Identifying candidate nodes for phase assignment in a logic network Grant 6,035,110 - Puri , et al. March 7, 2	2000-03-07
Methodology and apparatus for modular partitioning for the machine design of asynchronous circuits Grant 5,469,367 - Puri , et al. November 21, 1	1995-11-21

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