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Patent applications and USPTO patent grants for Pugliesi-Conti; Paul-Henri.The latest application filed is for "testing of asynchronous reset logic".
Patent | Date |
---|---|
Testing of asynchronous reset logic Grant 11,301,607 - Waayers , et al. April 12, 2 | 2022-04-12 |
Testing Of Asynchronous Reset Logic App 20210109153 - Waayers; Tom ;   et al. | 2021-04-15 |
Circuit for securing scan chain data Grant 9,746,519 - Pugliesi-Conti August 29, 2 | 2017-08-29 |
Secure low pin count scan Grant 9,170,297 - Pugliesi-Conti October 27, 2 | 2015-10-27 |
Secure Low Pin Count Scan App 20130166977 - Pugliesi-Conti; Paul-Henri | 2013-06-27 |
Circuit for Securing Scan Chain Data App 20120246528 - Pugliesi-Conti; Paul-Henri | 2012-09-27 |
Multi-clock system-on-chip with universal clock control modules for transition fault test at speed multi-core Grant 7,900,108 - Pugliesi-Conti , et al. March 1, 2 | 2011-03-01 |
Multi-clock System-on-chip With Universal Clock Control Modules For Transition Fault Test At Speed Multi-core App 20100011264 - Pugliesi-Conti; Paul-Henri ;   et al. | 2010-01-14 |
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