loadpatents
name:-0.0088150501251221
name:-0.0087990760803223
name:-0.0021238327026367
Prudvi; Venkatasreekanth Patent Filings

Prudvi; Venkatasreekanth

Patent Applications and Registrations

Patent applications and USPTO patent grants for Prudvi; Venkatasreekanth.The latest application filed is for "self-moderating bus arbitration architecture".

Company Profile
1.7.7
  • Prudvi; Venkatasreekanth - Bangalore IN
  • Prudvi; Venkatasreekanth - Pradesh IN
  • Prudvi; Venkatasreekanth - KrishnaDT
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Self-moderating bus arbitration architecture
Grant 10,521,381 - GopalaKrishnaSetty , et al. Dec
2019-12-31
Self-moderating Bus Arbitration Architecture
App 20190278728 - GopalaKrishnaSetty; Raghu G. ;   et al.
2019-09-12
Self-moderating bus arbitration architecture
Grant 10,303,631 - GopalaKrishnaSetty , et al.
2019-05-28
Slew Window Shift Placement Method To Reduce Hot Spots And Recover Vt/area
App 20180089354 - Chandra; Alok ;   et al.
2018-03-29
Area and/or power optimization through post-layout modification of integrated circuit (IC) design blocks
Grant 9,852,259 - Bickford , et al. December 26, 2
2017-12-26
Self-moderating Bus Arbitration Architecture
App 20170270066 - GopalaKrishnaSetty; Raghu G. ;   et al.
2017-09-21
Temperature-aware integrated circuit design methods and systems
Grant 9,767,240 - Bickford , et al. September 19, 2
2017-09-19
Electromigration-aware integrated circuit design methods and systems
Grant 9,740,815 - Bickford , et al. August 22, 2
2017-08-22
Area And/or Power Optimization Through Post-layout Modification Of Integrated Circuit (ic) Design Blocks
App 20170212977 - Bickford; Jeanne P. ;   et al.
2017-07-27
Temperature-aware Integrated Circuit Design Methods And Systems
App 20170147727 - Bickford; Jeanne P. ;   et al.
2017-05-25
Electromigration-aware Integrated Circuit Design Methods And Systems
App 20170116367 - Bickford; Jeanne P. ;   et al.
2017-04-27
System and method to speed up PLL lock time on subsequent calibrations via stored band values
Grant 9,571,111 - Cranford, Jr. , et al. February 14, 2
2017-02-14
Method and system for automatically accessing internal signals or ports in a design hierarchy
Grant 8,001,503 - Basappa , et al. August 16, 2
2011-08-16
Method And System For Automatically Accessing Internal Signals Or Ports In A Design Hierarchy
App 20090158225 - Basappa; Jayashri Arsikere ;   et al.
2009-06-18

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