loadpatents
name:-0.034353971481323
name:-0.037478923797607
name:-0.00063490867614746
ProMOS Technologies PTE. Ltd. Patent Filings

ProMOS Technologies PTE. Ltd.

Patent Applications and Registrations

Patent applications and USPTO patent grants for ProMOS Technologies PTE. Ltd..The latest application filed is for "dual bit line precharge architecture and method for low power dynamic random access memory (dram) integrated circuit devices and devices incorporating embedded dram".

Company Profile
0.32.29
  • ProMOS Technologies PTE. Ltd. - Singapore SG
  • Promos Technologies Pte. Ltd - Districentre SG
  • ProMOS Technologies PTE.LTD. - ODC Districentre SG
  • ProMOS Technologies Pte. Ltd - Singapore SG
  • ProMOS Technologies Pte. Ltd. -
  • PROMOS TECHNOLOGIES PTE.LTD. - SG
  • PROMOS TECHNOLOGIES PTE.LTD. - 30 Toh Guan Road #08-09 ODC Districentre Singapore SG
  • Promos Technologies Pte. Ltd. - Districentre SG
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Shielding of datalines with physical placement based on time staggered access
Grant 8,594,114 - Faue November 26, 2
2013-11-26
Dual bit line precharge architecture and method for low power dynamic random access memory (DRAM) integrated circuit devices and devices incorporating embedded DRAM
Grant 8,339,882 - Parris , et al. December 25, 2
2012-12-25
Semiconductor devices with gate electrodes and with monocrystalline silicon regions that contain atoms of nitrogen and one or more of chlorine, bromine, sulfur, fluorine, or phosphorus
Grant 8,283,733 - Dong , et al. October 9, 2
2012-10-09
Non-volatile memory devices with charge storage regions
Grant 8,125,020 - He , et al. February 28, 2
2012-02-28
Dual Bit Line Precharge Architecture And Method For Low Power Dynamic Random Access Memory (dram) Integrated Circuit Devices And Devices Incorporating Embedded Dram
App 20120008445 - Parris; Michael C. ;   et al.
2012-01-12
Dual Bit Line Precharge Architecture And Method For Low Power Dynamic Random Access Memory (dram) Integrated Circuit Devices And Devices Incorporating Embedded Dram
App 20120008444 - Parris; Michael C. ;   et al.
2012-01-12
Twin cell architecture for integrated circuit dynamic random access memory (DRAM) devices and those devices incorporating embedded DRAM
Grant 7,916,567 - Parris , et al. March 29, 2
2011-03-29
N-bit shift register controller
Grant 7,889,831 - Mnich February 15, 2
2011-02-15
Using differential data strobes in non-differential mode to enhance data capture window
Grant 7,889,579 - Faue February 15, 2
2011-02-15
Configurable architecture hybrid analog/digital delay locked loop (DLL) and technique with fast open loop digital locking for integrated circuit devices
Grant 7,876,137 - Heightley January 25, 2
2011-01-25
Method of repairing deep subsurface defects in a silicon substrate that includes diffusing negatively charged ions into the substrate from a sacrificial oxide layer
Grant 7,851,339 - Dong , et al. December 14, 2
2010-12-14
Asymetric data path position and delays technique enabling high speed access in integrated circuit memory devices
Grant 7,830,734 - Faue November 9, 2
2010-11-09
Methods for inspecting and optionally reworking summed photolithography patterns resulting from plurally-overlaid patterning steps during mass production of semiconductor devices
Grant 7,829,168 - Zhang , et al. November 9, 2
2010-11-09
Nonvolatile memories with laterally recessed charge-trapping dielectric
Grant 7,816,726 - He , et al. October 19, 2
2010-10-19
Integrated circuits with substrate protrusions, including (but not limited to) floating gate memories
Grant 7,808,032 - He , et al. October 5, 2
2010-10-05
Fabrication of integrated circuits with isolation trenches
Grant 7,807,577 - Dong , et al. October 5, 2
2010-10-05
High capacitive load and noise tolerant system and method for controlling the drive strength of output drivers in integrated circuit devices
Grant 7,782,080 - Eaton August 24, 2
2010-08-24
Photolithography with optical masks having more transparent features surrounded by less transparent features
Grant 7,771,903 - Zhang , et al. August 10, 2
2010-08-10
Multi-bank block architecture for integrated circuit memory devices having non-shared sense amplifier bands between banks
Grant 7,764,565 - Faue July 27, 2
2010-07-27
Nonvolatile memories with tunnel dielectric with chlorine
Grant 7,737,487 - Dong , et al. June 15, 2
2010-06-15
Configurable Architecture Hybrid Analog/digital Delay Locked Loop (dll) And Technique With Fast Open Loop Digital Locking For Integrated Circuit Devices
App 20100123494 - Heightley; John D.
2010-05-20
High Capacitive Load And Noise Tolerant System And Method For Controlling The Drive Strength Of Output Drivers In Integrated Circuit Devices
App 20100060315 - Eaton; Steve
2010-03-11
Shielding Of Datalines With Physical Placement Based On Time Staggered Access
App 20090300255 - Faue; Jon
2009-12-03
Low Skew Differential Amplifier Using Tail Voltage Reference And Tail Feedback
App 20090237162 - Jones, JR.; Oscar Frederick
2009-09-24
Multi-bank Block Architecture For Integrated Circuit Memory Devices Having Non-shared Sense Amplifier Bands Between Banks
App 20090231944 - Faue; Jon Allan
2009-09-17
Assymetric Data Path Position And Delays Technique Enabling High Speed Access In Integrated Circuit Memory Devices
App 20090231945 - Faue; Jon Allan
2009-09-17
Twin Cell Architecture For Integrated Circuit Dynamic Random Access Memory (dram) Devices And Those Devices Incorporating Embedded Dram
App 20090225613 - Parris; Michael C. ;   et al.
2009-09-10
Low skew differential amplifier using tail voltage reference and tail feedback
Grant 7,583,142 - Jones, Jr. September 1, 2
2009-09-01
High-speed, low-power input buffer for integrated circuit devices
Grant 7,583,110 - Butler September 1, 2
2009-09-01
Automatic duty cycle correction circuit with programmable duty cycle target
Grant 7,570,094 - Mnich August 4, 2
2009-08-04
Using Differential Data Strobes In Non-differential Mode To Enhance Data Capture Window
App 20090190410 - Faue; Jon
2009-07-30
N-bit Shift Register Controller
App 20090154286 - Mnich; Christopher M.
2009-06-18
Nonvolatile Memories Which Combine A Dielectric, Charge-trapping Layer With A Floating Gate
App 20090096009 - Dong; Zhong ;   et al.
2009-04-16
Circuit and technique for adjusting and accurately controlling clock duty cycles in integrated circuit devices
Grant 7,518,425 - Heightley April 14, 2
2009-04-14
Refresh period adjustment technique for dynamic random access memories (DRAM) and integrated circuit devices incorporating embedded DRAM
Grant 7,515,494 - Butler April 7, 2
2009-04-07
Use of multiple voltage controlled delay lines for precise alignment and duty cycle control of the data output of a DDR memory device
Grant 7,474,136 - Heightley January 6, 2
2009-01-06
Method for Achieving Uniform Chemical Mechanical Polishing In Integrated Circuit Manufacturing
App 20080318428 - Ding; Yi ;   et al.
2008-12-25
Automatic Duty Cycle Correction Circuit With Programmable Duty Cycle Target
App 20080315929 - Mnich; Christopher M.
2008-12-25
Wide Window Clock Scheme For Loading Output Fifo Registers
App 20080291748 - Faue; Jon Allan ;   et al.
2008-11-27
Wide Window Clock Scheme For Loading Output Fifo Registers
App 20080285371 - Faue; Jon Allan ;   et al.
2008-11-20
Use Of Multiple Voltage Controlled Delay Lines For Precise Alignment And Duty Cycle Control Of The Data Output Of A Ddr Memory Device
App 20080278211 - Heightley; John D.
2008-11-13
Integrated Circuits With Substrate Protrusions, Including (but Not Limited To) Floating Gate Memories
App 20080266949 - He; Yue-Song ;   et al.
2008-10-30
Wide window clock scheme for loading output FIFO registers
Grant 7,440,351 - Faue , et al. October 21, 2
2008-10-21
Method To Regulate Propagation Delay Of Capacitively Coupled Parallel Lines
App 20080204102 - Meadows; Harold Brett
2008-08-28
Circuit And Technique For Adjusting And Accurately Controlling Clock Duty Cycles In Integrated Circuit Devices
App 20080186068 - Heightley; John D.
2008-08-07
Reducing nitrogen concentration with in-situ steam generation
Grant 7,387,972 - Dong , et al. June 17, 2
2008-06-17
Refresh Period Adjustment Technique For Dynamic Random Access Memories (dram) And Integrated Circuit Devices Incorporating Embedded Dram
App 20080112248 - Butler; Douglas B.
2008-05-15
Use of TEOS oxides in integrated circuit fabrication processes
Grant 7,371,695 - Lee , et al. May 13, 2
2008-05-13
Fabrication of semiconductor device exhibiting reduced dielectric loss in isolation trenches
Grant 7,355,239 - Haselden , et al. April 8, 2
2008-04-08
Self-aligned contacts to source/drain regions
App 20080023748 - Ding; Yi
2008-01-31
Use Of Teos Oxides In Integrated Circuit Fabrication Processes
App 20070290292 - Lee; Tai-Peng ;   et al.
2007-12-20
Method for achieving uniform chemical mechanical polishing in integrated circuit manufacturing
App 20070264827 - Ding; Yi ;   et al.
2007-11-15
Method for providing STI structures with high coupling ratio in integrated circuit manufacturing
App 20070262476 - Ding; Yi ;   et al.
2007-11-15
Reducing nitrogen concentration with in-situ steam generation
App 20070207627 - Dong; Zhong ;   et al.
2007-09-06
High-speed, Low-power Input Buffer For Integrated Circuit Devices
App 20070176650 - Butler; Douglas Blaine
2007-08-02
High-speed, low-power input buffer for integrated circuit devices
Grant 7,250,795 - Butler July 31, 2
2007-07-31
Use of TEOS oxides in integrated circuit fabrication processes
App 20070155189 - Lee; Tai-Peng ;   et al.
2007-07-05
Shielded Bitline Architecture For Dynamic Random Access Memory (dram) Arrays
App 20070121414 - Butler; Douglas Blaine
2007-05-31
Corner protection to reduce wrap around
Grant 7,196,381 - Hsiao , et al. March 27, 2
2007-03-27
Multistage parallel-to-serial conversion of read data in memories, with the first serial bit skipping at least one stage
Grant 7,054,215 - Kwon , et al. May 30, 2
2006-05-30
Data sorting in memories
Grant 7,016,235 - Faue , et al. March 21, 2
2006-03-21

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