| Patent | Date |
|---|
Operand pool instruction reservation clustering in a scheduler circuit in a processor
Grant 11,392,410 - Priyadarshi , et al. July 19, 2 | 2022-07-19 |
Predicting load-based control independent (CI) register data independent (DI) (CIRDI) instructions as CI memory data dependent (DD) (CIMDD) instructions for replay in speculative misprediction recovery in a processor
Grant 11,392,387 - Kothinti Naresh , et al. July 19, 2 | 2022-07-19 |
Opportunistic consumer instruction steering based on producer instruction value prediction in a multi-cluster processor
Grant 11,327,763 - Perais , et al. May 10, 2 | 2022-05-10 |
Predicting Load-based Control Independent (ci) Register Data Independent (di) (cirdi) Instructions As Ci Memory Data Dependent (dd) (cimdd) Instructions For Replay In Speculative Misprediction Recovery In A Processor
App 20220137977 - KOTHINTI NARESH; Vignyan Reddy ; et al. | 2022-05-05 |
Restoring Speculative History Used For Making Speculative Predictions For Instructions Processed In A Processor Employing Control Independence Techniques
App 20220113976 - KOTHINTI NARESH; Vignyan Reddy ; et al. | 2022-04-14 |
Opportunistic Consumer Instruction Steering Based On Producer Instruction Value Prediction In A Multi-cluster Processor
App 20210389951 - PERAIS; Arthur ; et al. | 2021-12-16 |
Operand Pool Instruction Reservation Clustering In A Scheduler Circuit In A Processor
App 20210318905 - PRIYADARSHI; Shivam ; et al. | 2021-10-14 |
Performing flush recovery using parallel walks of sliced reorder buffers (SROBs)
Grant 11,113,068 - Tekmen , et al. September 7, 2 | 2021-09-07 |
Recovering register mapping state of a flushed instruction employing a snapshot of another register mapping state and traversing reorder buffer (ROB) entries in a processor
Grant 11,061,677 - Seth , et al. July 13, 2 | 2021-07-13 |
Deferring cache state updates in a non-speculative cache memory in a processor-based system in response to a speculative data request until the speculative data request becomes non-speculative
Grant 11,061,824 - Kothinti Naresh , et al. July 13, 2 | 2021-07-13 |
Limiting replay of load-based control independent (CI) instructions in speculative misprediction recovery in a processor
Grant 11,061,683 - Kothinti Naresh , et al. July 13, 2 | 2021-07-13 |
Systems and methods for processing instructions having wide immediate operands
Grant 11,036,512 - Perais , et al. June 15, 2 | 2021-06-15 |
Latency-based instruction reservation station clustering in a scheduler circuit in a processor
Grant 11,023,243 - Tekmen , et al. June 1, 2 | 2021-06-01 |
Systems And Methods For Processing Instructions Having Wide Immediate Operands
App 20210089308 - PERAIS; Arthur ; et al. | 2021-03-25 |
Deferring Cache State Updates In A Non-speculative Cache Memory In A Processor-based System In Response To A Speculative Data Request Until The Speculative Data Request Becomes Non-speculative
App 20210064541 - KOTHINTI NARESH; Vignyan Reddy ; et al. | 2021-03-04 |
Latency-based Instruction Reservation Clustering In A Scheduler Circuit In A Processor
App 20210026639 - TEKMEN; Yusuf Cagatay ; et al. | 2021-01-28 |
Enabling early execution of move-immediate instructions having variable immediate value sizes in processor-based devices
Grant 10,896,041 - Priyadarshi , et al. January 19, 2 | 2021-01-19 |
Minimizing traversal of a processor reorder buffer (ROB) for register rename map table (RMT) state recovery for interrupted instruction recovery in a processor
Grant 10,877,768 - Priyadarshi , et al. December 29, 2 | 2020-12-29 |
Limiting Replay Of Load-based Control Independent (ci) Instructions In Speculative Misprediction Recovery In A Processor
App 20200394040 - KOTHINTI NARESH; Vignyan Reddy ; et al. | 2020-12-17 |
Providing late physical register allocation and early physical register release in out-of-order processor (OOP)-based devices implementing a checkpoint-based architecture
Grant 10,860,328 - Priyadarshi , et al. December 8, 2 | 2020-12-08 |
Allocating power between multiple central processing units (CPUs) in a multi-CPU processor based on total current availability and individual CPU quality-of-service (QoS) requirements
Grant 10,831,254 - Priyadarshi , et al. November 10, 2 | 2020-11-10 |
Reconfiguring execution pipelines of out-of-order (OOO) computer processors based on phase training and prediction
Grant 10,635,446 - Priyadarshi , et al. | 2020-04-28 |
Providing Late Physical Register Allocation And Early Physical Register Release In Out-of-order Processor (oop)-based Devices Im
App 20200097296 - Priyadarshi; Shivam ; et al. | 2020-03-26 |
Method and apparatus for dynamic clock and voltage scaling in a computer processor based on program phase
Grant 10,551,896 - Priyadarshi , et al. Fe | 2020-02-04 |
Adaptively Predicting Usefulness Of Prefetches Generated By Hardware Prefetch Engines In Processor-based Devices
App 20190370176 - Priyadarshi; Shivam ; et al. | 2019-12-05 |
Dynamic pipeline throttling using confidence-based weighting of in-flight branch instructions
Grant 10,474,462 - Priyadarshi , et al. Nov | 2019-11-12 |
Method, Apparatus, And System For Reducing Live Readiness Calculations In Reservation Stations
App 20190332385 - SMITH; Rodney Wayne ; et al. | 2019-10-31 |
Slice construction for pre-executing data dependent loads
Grant 10,379,863 - Priyadarshi , et al. A | 2019-08-13 |
Intelligent data prefetching using address delta prediction
Grant 10,303,608 - Al Sheikh , et al. | 2019-05-28 |
Slice Construction For Pre-executing Data Dependent Loads
App 20190087192 - PRIYADARSHI; Shivam ; et al. | 2019-03-21 |
ALLOCATING POWER BETWEEN MULTIPLE CENTRAL PROCESSING UNITS (CPUS) IN A MULTI-CPU PROCESSOR BASED ON TOTAL CURRENT AVAILABILITY AND INDIVIDUAL CPU QUALITY-OF-SERVICE (QoS) REQUIREMENTS
App 20190086982 - Priyadarshi; Shivam ; et al. | 2019-03-21 |
Selective bypassing of allocation in a cache
Grant 10,223,278 - Priyadarshi , et al. | 2019-03-05 |
Providing references to previously decoded instructions of recently-provided instructions to be executed by a processor
Grant 10,223,118 - Naresh , et al. | 2019-03-05 |
Expediting Cache Misses Through Cache Hit Prediction
App 20190065384 - AL SHEIKH; Rami Mohammad ; et al. | 2019-02-28 |
Intelligent Data Prefetching Using Address Delta Prediction
App 20190065375 - AL SHEIKH; Rami Mohammad ; et al. | 2019-02-28 |
Filtering Insertion Of Evicted Cache Entries Predicted As Dead-on-arrival (doa) Into A Last Level Cache (llc) Memory Of A Cache Memory System
App 20190034354 - Priyadarshi; Shivam | 2019-01-31 |
Cost-aware cache replacement
Grant 10,185,668 - Al Sheikh , et al. Ja | 2019-01-22 |
Cost-aware Cache Replacement
App 20190018798 - AL SHEIKH; Rami Mohammad ; et al. | 2019-01-17 |
Selective Refresh Mechanism For Dram
App 20190013062 - ATALLAH; Francois Ibrahim ; et al. | 2019-01-10 |
Reducing memory access bandwidth based on prediction of memory request size
Grant 10,169,240 - Dwiel , et al. J | 2019-01-01 |
Storing narrow produced values for instruction operands directly in a register map in an out-of-order processor
Grant 10,108,417 - Krishna , et al. October 23, 2 | 2018-10-23 |
Method And Apparatus For Dynamic Clock And Voltage Scaling In A Computer Processor Based On Program Phase
App 20180074568 - PRIYADARSHI; Shivam ; et al. | 2018-03-15 |
Method and apparatus for dynamic clock and voltage scaling in a computer processor based on program phase
Grant 9,851,774 - Priyadarshi , et al. December 26, 2 | 2017-12-26 |
Selective storing of previously decoded instructions of frequently-called instruction sequences in an instruction sequence buffer to be executed by a processor
Grant 9,830,152 - Kothinti Naresh , et al. November 28, 2 | 2017-11-28 |
Selective Bypassing Of Allocation In A Cache
App 20170293565 - PRIYADARSHI; Shivam ; et al. | 2017-10-12 |
Reducing Memory Access Bandwidth Based On Prediction Of Memory Request Size
App 20170293561 - DWIEL; Brandon Harley Anthony ; et al. | 2017-10-12 |
Cost-aware Cache Replacement
App 20170293571 - AL SHEIKH; Rami Mohammad A. ; et al. | 2017-10-12 |
Providing References To Previously Decoded Instructions Of Recently-provided Instructions To Be Executed By A Processor
App 20170277536 - Kothinti Naresh; Vignyan Reddy ; et al. | 2017-09-28 |
Dynamic Pipeline Throttling Using Confidence-based Weighting Of In-flight Branch Instructions
App 20170249149 - PRIYADARSHI; Shivam ; et al. | 2017-08-31 |
Method And Apparatus For Dynamic Clock And Voltage Scaling In A Computer Processor Based On Program Phase
App 20170192484 - Priyadarshi; Shivam ; et al. | 2017-07-06 |
Selective Storing Of Previously Decoded Instructions Of Frequently-called Instruction Sequences In An Instruction Sequence Buffer To Be Executed By A Processor
App 20170177366 - Kothinti Naresh; Vignyan Reddy ; et al. | 2017-06-22 |
Method And Apparatus For Effective Clock Scaling At Exposed Cache Stalls
App 20170090508 - PRIYADARSHI; Shivam ; et al. | 2017-03-30 |
Reconfiguring Execution Pipelines Of Out-of-order (ooo) Computer Processors Based On Phase Training And Prediction
App 20170090930 - Priyadarshi; Shivam ; et al. | 2017-03-30 |
Method And Apparatus For Dynamically Tuning Speculative Optimizations Based On Instruction Signature
App 20170090936 - AL SHEIKH; Rami Mohammad ; et al. | 2017-03-30 |
Hierarchical Register File System
App 20170060593 - KRISHNA; Anil ; et al. | 2017-03-02 |
Power Efficient Fetch Adaptation
App 20170046159 - PRIYADARSHI; Shivam ; et al. | 2017-02-16 |
Storing Narrow Produced Values For Instruction Operands Directly In A Register Map In An Out-of-order Processor
App 20170046154 - Krishna; Anil ; et al. | 2017-02-16 |
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