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Channel training using a replica lane
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Low power VTT generation mechanism for receiver termination
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Channel Training Using A Replica Lane
App 20170373944 - Lackey, JR.; Stanley Ames ; et al. | 2017-12-28 |
Asynchronous Feedback Training
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Common mode extraction and tracking for data signaling
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Integrated Controller For Training Memory Physical Layer Interface
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Memory System Components For Split Channel Architecture
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System and method of data communications between electronic devices
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Method and Apparatus for Memory Access Delay Training
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Method and apparatus for using DFE in a system with non-continuous data
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Ddr Receiver Enable Cycle Training
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System And Method Of Data Communications Between Electronic Devices
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Method And Apparatus For Using Dfe In A System With Non-continuous Data
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Generating a transmission clock signal and a reception clock signal for a transceiver using an oscillator
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Clock signal extraction device and method for extracting a clock signal from data signal
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Method and arrangement for generating an output clock signal with an adjustable phase relation from a plurality of input clock signals
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Concept for interfacing a first circuit requiring a first supply voltage and a second supply circuit requiring a second supply voltage
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Apparatus and method for providing a signal for transmission via a signal line
App 20080155150 - Prete; Edoardo ; et al. | 2008-06-26 |
Concept For Interfacing A First Circuit Requiring A First Supply Voltage And A Second Supply Circuit Requiring A Second Supply Voltage
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Memory buffer and method for buffering data
App 20080126624 - Prete; Edoardo ; et al. | 2008-05-29 |
Apparatus and method for switching an apparatus to a power saving mode
App 20080126816 - Prete; Edoardo ; et al. | 2008-05-29 |
Apparatus and method for transmitting signals over a signal line
App 20080123792 - Prete; Edoardo ; et al. | 2008-05-29 |
Data sampler including a first stage and a second stage
App 20080024215 - Gopalakrishnan; Karthik ; et al. | 2008-01-31 |
Method and apparatus for phase detection
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Memory system with a retiming circuit and a method of exchanging data and timing signals between a memory controller and a memory device
App 20070288716 - Prete; Edoardo ; et al. | 2007-12-13 |
Clock and data recovery circuit having gain control
App 20070183553 - Sanders; Anthony Fraser ; et al. | 2007-08-09 |
Clock and data recovery circuit including first and second stages
App 20070183552 - Sanders; Anthony Fraser ; et al. | 2007-08-09 |
Receiving data over channels with intersymbol interference
App 20070177702 - Sanders; Anthony Fraser ; et al. | 2007-08-02 |
Method and arrangement for generating an output clock signal with an adjustable phase relation from a plurality of input clock signals
App 20060029172 - Andreotti; Claudio ; et al. | 2006-02-09 |
Clock signal extraction device and method for extraction a clock signal from data signal
App 20060023827 - Sanders; Anthony ; et al. | 2006-02-02 |
Method and arrangement for frequency doubling
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Method and apparatus for phase detection
App 20040001566 - Gregorius, Peter ; et al. | 2004-01-01 |
Method and arrangement for frequency doubling
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