| Patent | Date |
|---|
Multiple gate transistor having homogenously silicided fin end portions
Grant 8,791,509 - Beyer , et al. July 29, 2 | 2014-07-29 |
Technique for exposing a placeholder material in a replacement gate approach by modifying a removal rate of stressed dielectric overlayers
Grant 8,357,575 - Hempel , et al. January 22, 2 | 2013-01-22 |
Technique For Exposing A Placeholder Material In A Replacement Gate Approach By Modifying A Removal Rate Of Stressed Dielectric Overlayers
App 20120282764 - Hempel; Klaus ; et al. | 2012-11-08 |
Semiconductor device comprising a metal gate stack of reduced height and method of forming the same
Grant 8,293,610 - Beyer , et al. October 23, 2 | 2012-10-23 |
Technique for exposing a placeholder material in a replacement gate approach by modifying a removal rate of stressed dielectric overlayers
Grant 8,247,281 - Hempel , et al. August 21, 2 | 2012-08-21 |
Drive current adjustment for transistors by local gate engineering
Grant 8,188,871 - Horstmann , et al. May 29, 2 | 2012-05-29 |
Maintaining Integrity of a High-K Gate Stack After Embedding a Stressor Material by Using a Liner
App 20110266625 - Carter; Richard ; et al. | 2011-11-03 |
Semiconductor device comprising NMOS and PMOS transistors with embedded Si/Ge material for creating tensile and compressive strain
Grant 8,039,335 - Beyer , et al. October 18, 2 | 2011-10-18 |
Semiconductor Device Comprising Nmos And Pmos Transistors With Embedded Si/ge Material For Creating Tensile And Compressive Strain
App 20110104878 - Beyer; Sven ; et al. | 2011-05-05 |
Semiconductor device comprising NMOS and PMOS transistors with embedded Si/Ge material for creating tensile and compressive strain
Grant 7,893,503 - Beyer , et al. February 22, 2 | 2011-02-22 |
Technique For Exposing A Placeholder Material In A Replacement Gate Approach By Modifying A Removal Rate Of Stressed Dielectric Overlayers
App 20100330790 - Hempel; Klaus ; et al. | 2010-12-30 |
Technique for forming an isolation trench as a stress source for strain engineering
Grant 7,833,874 - Frohberg , et al. November 16, 2 | 2010-11-16 |
Transistor having a locally provided metal silicide region in contact areas and a method of forming the transistor
Grant 7,799,682 - Beyer , et al. September 21, 2 | 2010-09-21 |
Semiconductor Device Comprising Nmos And Pmos Transistors With Embedded Si/ge Material For Creating Tensile And Compressive Strain
App 20100187635 - BEYER; SVEN ; et al. | 2010-07-29 |
Methods for fabricating low contact resistance CMOS circuits
Grant 7,754,554 - Peidous , et al. July 13, 2 | 2010-07-13 |
Technique for locally adapting transistor characteristics by using advanced laser/flash anneal techniques
Grant 7,745,334 - Press , et al. June 29, 2 | 2010-06-29 |
Semiconductor device comprising NMOS and PMOS transistors with embedded Si/Ge material for creating tensile and compressive strain
Grant 7,741,167 - Beyer , et al. June 22, 2 | 2010-06-22 |
Multiple Gate Transistor Having Homogenously Silicided Fin End Portions
App 20100133614 - Beyer; Sven ; et al. | 2010-06-03 |
Drive Current Adjustment For Transistors By Local Gate Engineering
App 20100025776 - Horstmann; Manfred ; et al. | 2010-02-04 |
Field effect transistors and methods for fabricating the same
Grant 7,605,045 - Peidous , et al. October 20, 2 | 2009-10-20 |
Semiconductor Device Comprising A Metal Gate Stack Of Reduced Height And Method Of Forming The Same
App 20090218639 - Beyer; Sven ; et al. | 2009-09-03 |
Method For Forming A Deep Trench In An Soi Device By Reducing The Shielding Effect Of The Active Layer During The Deep Trench Etch Process
App 20090032855 - Press; Patrick ; et al. | 2009-02-05 |
Method Of Forming A Semiconductor Structure Comprising An Implantation Of Ions In A Material Layer To Be Etched
App 20080299733 - Press; Patrick ; et al. | 2008-12-04 |
Methods For Fabricating Low Contact Resistance Cmos Circuits
App 20080182370 - Peidous; Igor ; et al. | 2008-07-31 |
Technique for reducing silicide defects by reducing deleterious effects of particle bombardment prior to silicidation
Grant 7,384,877 - Kahlert , et al. June 10, 2 | 2008-06-10 |
Semiconductor Device Comprising Nmos And Pmos Transistors With Embedded Si/ge Material For Creating Tensile And Compressive Strain
App 20080099794 - Beyer; Sven ; et al. | 2008-05-01 |
Technique For Locally Adapting Transistor Characteristics By Using Advanced Laser/flash Anneal Techniques
App 20080081471 - Press; Patrick ; et al. | 2008-04-03 |
Transistor Having A Locally Provided Metal Silicide Region In Contact Areas And A Method Of Forming The Transistor
App 20080054371 - Beyer; Sven ; et al. | 2008-03-06 |
Field Effect Transistors And Methods For Fabricating The Same
App 20080014704 - Peidous; Igor ; et al. | 2008-01-17 |
Method Of Increasing Transistor Performance By Dopant Activation After Silicidation
App 20070281472 - Press; Patrick ; et al. | 2007-12-06 |
Formation Of Silicided Surfaces For Silicon/carbon Source/drain Regions
App 20070200176 - Kammler; Thorsten ; et al. | 2007-08-30 |
Technique For Forming An Isolation Trench As A Stress Source For Strain Engineering
App 20070155121 - Frohberg; Kai ; et al. | 2007-07-05 |
Technique For Reducing Silicide Defects By Reducing Deleterious Effects Of Particle Bombardment Prior To Silicidation
App 20070045226 - Kahlert; Volker ; et al. | 2007-03-01 |
Technique For Reducing Silicide Non-uniformities By Adapting A Vertical Dopant Profile
App 20060270202 - Wirbeleit; Frank ; et al. | 2006-11-30 |
Method of boron doping wafers using a vertical oven system
Grant 6,548,378 - Boness , et al. April 15, 2 | 2003-04-15 |
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