PRENER; Daniel Arthur

Patent Applications and Registrations

Patent applications and USPTO patent grants for PRENER; Daniel Arthur.The latest application filed is for "processor core, processor and method for executing a composite scalar-vector very lare instruction word (vliw) instruction".

Company Profile

1.13.12

PRENER; Daniel Arthur - Croton-on-Hudson NY
Prener; Daniel Arthur - Briarcliff Manor NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Processor Core, Processor and Method for Executing a Composite Scalar-Vector Very Lare Instruction Word (VLIW) Instruction App 20200142704 - Fleischer; Bruce M. ; et al.	2020-05-07
Executing a composite VLIW instruction having a scalar atom that indicates an iteration of execution Grant 10,572,263 - Fleischer , et al. Feb	2020-02-25
Processor Core, Processor And Method For Executing A Composite Scalar-Vector Very Lare Instruction Word (VLIW) Instruction App 20170286108 - Fleischer; Bruce M. ; et al.	2017-10-05
Method and system for efficient emulation of multiprocessor memory consistency Grant 9,043,194 - Nair , et al. May 26, 2	2015-05-26
Method and system for efficient emulation of multiprocessor address translation on a multiprocessor Grant 8,719,548 - Altman , et al. May 6, 2	2014-05-06
Hybrid mechanism for more efficient emulation and method therefor Grant 8,578,351 - Nair , et al. November 5, 2	2013-11-05
Hybrid Mechanism For More Efficient Emulation And Method Therefor App 20120089820 - Nair; Ravi ; et al.	2012-04-12
Hybrid mechanism for more efficient emulation and method therefor Grant 8,108,843 - Nair , et al. January 31, 2	2012-01-31
Method And System For Efficient Emulation Of Multiprocessor Address Translation On A Multiprocessor App 20110191095 - Altman; Erik Richter ; et al.	2011-08-04
Compiler method for employing multiple autonomous synergistic processors to simultaneously operate on longer vectors of data Grant 7,962,906 - O'Brien , et al. June 14, 2	2011-06-14
Method and system for efficient emulation of multiprocessor address translation on a multiprocessor host Grant 7,953,588 - Altman , et al. May 31, 2	2011-05-31
Method and system for multiprocessor emulation on a multiprocessor host system Grant 7,844,446 - Altman , et al. November 30, 2	2010-11-30
Method And System For Multiprocessor Emulation On A Multiprocessor Host System App 20090157377 - Altman; Erik Richter ; et al.	2009-06-18
Method and system for multiprocessor emulation on a multiprocessor host system Grant 7,496,494 - Altman , et al. February 24, 2	2009-02-24
Compiler Method for Employing Multiple Autonomous Synergistic Processors to Simultaneously Operate on Longer Vectors of Data App 20080229298 - O'Brien; John Kevin Patrick ; et al.	2008-09-18
Method and system for transparent dynamic optimization in a multiprocessing environment Grant 7,146,607 - Nair , et al. December 5, 2	2006-12-05
Method and apparatus for embedding wide instruction words in a fixed-length instruction set architecture App 20060174089 - Altman; Erik Richter ; et al.	2006-08-03
Method and system for efficient emulation of multiprocessor memory consistency App 20040078186 - Nair, Ravi ; et al.	2004-04-22
Method and system for transparent dynamic optimization in a multiprocessing environment App 20040054992 - Nair, Ravi ; et al.	2004-03-18
Method and system for multiprocessor emulation on a multiprocessor host system App 20040054517 - Altman, Erik Richter ; et al.	2004-03-18
Method and system for efficient emulation of multiprocessor address translation on a multiprocessor host App 20040054518 - Altman, Erik Richter ; et al.	2004-03-18
Hybrid mechanism for more efficient emulation and method therefor App 20040054993 - Nair, Ravi ; et al.	2004-03-18

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