loadpatents
name:-0.027462959289551
name:-0.067016839981079
name:-0.0072779655456543
Preisler; Edward Patent Filings

Preisler; Edward

Patent Applications and Registrations

Patent applications and USPTO patent grants for Preisler; Edward.The latest application filed is for "method of manufacturing nickel silicide in bipolar complementary-metal-oxide-semiconductor (bicmos)".

Company Profile
7.24.30
  • Preisler; Edward - San Clemente CA
  • Preisler; Edward - Newport Beach CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Semiconductor structure having group III-V device on group IV substrate
Grant 11,349,280 - Preisler , et al. May 31, 2
2022-05-31
Semiconductor structure having group III-V chiplet on group IV substrate and cavity in proximity to heating element
Grant 11,296,482 - Preisler , et al. April 5, 2
2022-04-05
Nickel silicide in bipolar complementary-metal-oxide-semiconductor (BiCMOS) device and method of manufacturing
Grant 11,276,682 - Sinha , et al. March 15, 2
2022-03-15
Germanium on insulator for CMOS imagers in the short wave infrared
Grant 11,271,028 - Levy , et al. March 8, 2
2022-03-08
Method of Manufacturing Bipolar Complementary-Metal-Oxide-Semiconductor (BiCMOS) Devices Using Nickel Silicide
App 20220068914 - Sinha; Mantavya ;   et al.
2022-03-03
Nickel Silicide in Bipolar Complementary-Metal-Oxide-Semiconductor (BiCMOS) Device
App 20220068913 - Sinha; Mantavya ;   et al.
2022-03-03
Nickel Silicide in Bipolar Complementary-Metal-Oxide-Semiconductor (BiCMOS) Device and Method of Manufacturing
App 20220068911 - Sinha; Mantavya ;   et al.
2022-03-03
Method of Manufacturing Nickel Silicide in Bipolar Complementary-Metal-Oxide-Semiconductor (BiCMOS)
App 20220068912 - Sinha; Mantavya ;   et al.
2022-03-03
Fabrication of semiconductor structure having group III-V device on group IV substrate with separately formed contacts using different metal liners
Grant 11,233,159 - Preisler , et al. January 25, 2
2022-01-25
Semiconductor structure having porous semiconductor segment for RF devices and bulk semiconductor region for non-RF devices
Grant 11,195,920 - Hurwitz , et al. December 7, 2
2021-12-07
Method for Forming a Semiconductor Structure Having a Porous Semiconductor Layer in RF Devices
App 20210375618 - Hurwitz; Paul D. ;   et al.
2021-12-02
Semiconductor structure having porous semiconductor layer for RF devices
Grant 11,164,740 - Hurwitz , et al. November 2, 2
2021-11-02
Anode up--cathode down silicon and germanium photodiode
Grant 11,081,610 - Zhu , et al. August 3, 2
2021-08-03
Semiconductor Structure Having Group III-V Device on Group IV Substrate and Contacts with Liner Stacks
App 20210217903 - Preisler; Edward ;   et al.
2021-07-15
Group III-V Device on Group IV Substrate Using Contacts with Precursor Stacks
App 20210217922 - Preisler; Edward ;   et al.
2021-07-15
Structure and Method for Process Control Monitoring for Group III-V Devices Integrated with Group IV Substrate
App 20210217908 - Preisler; Edward
2021-07-15
Fabrication of Semiconductor Structure Having Group III-V Device on Group IV Substrate with Separately Formed Contacts Using Different Metal Liners
App 20210217904 - Preisler; Edward ;   et al.
2021-07-15
Semiconductor Structure Having Group III-V Chiplet on Group IV Substrate and Cavity in Proximity to Heating Element
App 20210218225 - Preisler; Edward ;   et al.
2021-07-15
Semiconductor Structure Having Group III-V Device on Group IV Substrate and Contacts with Precursor Stacks
App 20210217921 - Preisler; Edward ;   et al.
2021-07-15
Semiconductor Structure Having Group III-V Device on Group IV Substrate
App 20210218219 - Preisler; Edward ;   et al.
2021-07-15
Integrated optical/electrical probe card for testing optical, electrical, and optoelectronic devices in a semiconductor die
Grant 10,996,081 - Qamar , et al. May 4, 2
2021-05-04
Semiconductor Structure Having Porous Semiconductor Layer for RF Devices
App 20210111019 - Hurwitz; Paul D. ;   et al.
2021-04-15
Semiconductor Structure Having Porous Semiconductor Segment for RF Devices and Bulk Semiconductor Region for Non-RF Devices
App 20210111249 - Hurwitz; Paul D. ;   et al.
2021-04-15
Method for fabrication of germanium photodiode with silicon cap
Grant 10,892,374 - Zhu , et al. January 12, 2
2021-01-12
Germanium photodiode with silicon cap
Grant 10,892,373 - Zhu , et al. January 12, 2
2021-01-12
Germanium On Insulator For Cmos Imagers In The Short Wave Infrared
App 20200365630 - Levy; Uriel ;   et al.
2020-11-19
Method for Fabrication of Germanium Photodiode with Silicon Cap
App 20200295220 - Zhu; Difeng ;   et al.
2020-09-17
Germanium Photodiode with Silicon Cap
App 20200259036 - A1
2020-08-13
Anode Up - Cathode Down Silicon and Germanium Photodiode
App 20200259037 - A1
2020-08-13
Silicon-on-insulator (SOI) die including a light emitting layer pedestal-aligned with a light receiving segment
Grant 10,649,137 - Preisler , et al.
2020-05-12
BiCMOS integration using a shared SiGe layer
Grant 10,297,591 - Preisler , et al.
2019-05-21
BiCMOS integration with reduced masking steps
Grant 10,290,630 - Preisler , et al.
2019-05-14
Ultra-broadband transimpedance amplifiers (tia) for optical fiber communications
Grant 10,243,523 - Heydari , et al.
2019-03-26
Ultra-broadband Transimpedance Amplifiers (tia) For Optical Fiber Communications
App 20180102749 - Heydari; Payam ;   et al.
2018-04-12
Structure and method for mitigating substrate parasitics in bulk high resistivity substrate technology
Grant 9,941,353 - Hurwitz , et al. April 10, 2
2018-04-10
Structure and Method for Mitigating Substrate Parasitics in Bulk High Resistivity Substrate Technology
App 20170338305 - Hurwitz; Paul D. ;   et al.
2017-11-23
Efficient fabrication of BiCMOS devices
Grant 9,673,191 - Preisler , et al. June 6, 2
2017-06-06
Isolated through silicon via and isolated deep silicon via having total or partial isolation
Grant 9,673,081 - Jebory , et al. June 6, 2
2017-06-06
Low-cost complementary BiCMOS integration scheme
Grant 9,640,528 - Preisler , et al. May 2, 2
2017-05-02
Isolated through silicon vias in RF technologies
Grant 9,577,035 - Hurwitz , et al. February 21, 2
2017-02-21
Semiconductor fabrication utilizing grating and trim masks
Grant 9,436,092 - Talor , et al. September 6, 2
2016-09-06
Heterojunction bipolar transistor having a germanium raised extrinsic base
Grant 9,209,264 - Preisler , et al. December 8, 2
2015-12-08
BiCMOS Integration with Reduced Masking Steps
App 20150303188 - Preisler; Edward ;   et al.
2015-10-22
Efficient Fabrication of BiCMOS Devices
App 20150303186 - Preisler; Edward ;   et al.
2015-10-22
Low-Cost Complementary BiCMOS Integration Scheme
App 20150303185 - Preisler; Edward ;   et al.
2015-10-22
BiCMOS Integration Using a Shared SiGe Layer
App 20150303187 - Preisler; Edward ;   et al.
2015-10-22
Heterojunction bipolar transistor having a germanium extrinsic base utilizing a sacrificial emitter post
Grant 9,064,886 - Preisler , et al. June 23, 2
2015-06-23
Heterojunction Bipolar Transistor having a Germanium Extrinsic Base Utilizing a Sacrificial Emitter Post
App 20140264458 - Preisler; Edward ;   et al.
2014-09-18
Heterojunction Bipolar Transistor having a Germanium Raised Extrinsic Base
App 20140264457 - Preisler; Edward ;   et al.
2014-09-18
Isolated Through Silicon Vias in RF Technologies
App 20140054743 - Hurwitz; Paul D. ;   et al.
2014-02-27
Isolated Through Silicon Via and Isolated Deep Silicon Via Having Total or Partial Isolation
App 20130313682 - Jebory; Hadi ;   et al.
2013-11-28
Semiconductor Fabrication Utilizing Grating and Trim Masks
App 20130256844 - Talor; George ;   et al.
2013-10-03
Method for integrating high voltage and high speed bipolar transistors on a substrate and related structure
Grant 7,968,417 - Preisler June 28, 2
2011-06-28
Method for integrating high voltage and high speed bipolar transistors on a substrate and related structure
App 20090085066 - Preisler; Edward
2009-04-02

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