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Patent applications and USPTO patent grants for Pranatharthi Haran; Balasubramanian S..The latest application filed is for "interconnects including dual-metal vias".
Patent | Date |
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Nanosheet transistors with sharp junctions Grant 11,430,651 - Cheng , et al. August 30, 2 | 2022-08-30 |
Vertical field effect transistor with bottom source-drain region Grant 11,355,633 - Reznicek , et al. June 7, 2 | 2022-06-07 |
Interconnects including dual-metal vias Grant 11,302,637 - Pranatharthi Haran , et al. April 12, 2 | 2022-04-12 |
Interconnects Including Dual-metal Vias App 20220051976 - Pranatharthi Haran; Balasubramanian S. ;   et al. | 2022-02-17 |
Subtractive RIE interconnect Grant 11,189,528 - Arnold , et al. November 30, 2 | 2021-11-30 |
Selective deposition with SAM for fully aligned via Grant 11,171,054 - Nguyen , et al. November 9, 2 | 2021-11-09 |
Self-aligned gate contact compatible cross couple contact formation Grant 11,164,782 - Xie , et al. November 2, 2 | 2021-11-02 |
Subtractive Rie Interconnect App 20210335665 - Arnold; John Christopher ;   et al. | 2021-10-28 |
Self-aligned isolation for nanosheet transistor Grant 11,152,464 - Pranatharthi Haran , et al. October 19, 2 | 2021-10-19 |
Selective Deposition With Sam For Fully Aligned Via App 20210313228 - Nguyen; Son ;   et al. | 2021-10-07 |
Self-aligned Isolation For Nanosheet Transistor App 20210305361 - Pranatharthi Haran; Balasubramanian S. ;   et al. | 2021-09-30 |
Late Gate Cut With Optimized Contact Trench Size App 20210305093 - Reznicek; Alexander ;   et al. | 2021-09-30 |
Late gate cut with optimized contact trench size Grant 11,133,217 - Reznicek , et al. September 28, 2 | 2021-09-28 |
Self-aligned Gate Contact Compatible Cross Couple Contact Formation App 20210210384 - Xie; Ruilong ;   et al. | 2021-07-08 |
Vertical Field Effect Transistor With Bottom Source-drain Region App 20210210632 - Reznicek; Alexander ;   et al. | 2021-07-08 |
Nanosheet transistors with sharp junctions Grant 10,600,638 - Cheng , et al. | 2020-03-24 |
Gate height and spacer uniformity Grant 10,586,741 - Cheng , et al. | 2020-03-10 |
Nanosheet Transistors With Sharp Junctions App 20180240871 - Cheng; Kangguo ;   et al. | 2018-08-23 |
Gate Height And Spacer Uniformity App 20180122710 - Cheng; Kangguo ;   et al. | 2018-05-03 |
Nanosheet Transistors With Sharp Junctions App 20180114834 - Cheng; Kangguo ;   et al. | 2018-04-26 |
Middle of line cobalt interconnection Grant 9,741,609 - Cheng , et al. August 22, 2 | 2017-08-22 |
Gate height and spacer uniformity Grant 9,704,991 - Cheng , et al. July 11, 2 | 2017-07-11 |
Methods of forming a combined gate and source/drain contact structure and the resulting device Grant 9,455,254 - Xie , et al. September 27, 2 | 2016-09-27 |
Methods Of Forming A Combined Gate And Source/drain Contact Structure And The Resulting Device App 20160133623 - Xie; Ruilong ;   et al. | 2016-05-12 |
Mixed lithography with dual resist and a single pattern transfer Grant 8,334,090 - Fuller , et al. December 18, 2 | 2012-12-18 |
Method and process for forming a self-aligned silicide contact Grant 8,101,518 - Cabral, Jr. , et al. January 24, 2 | 2012-01-24 |
Mixed Lithography With Dual Resist And A Single Pattern Transfer App 20110123779 - Fuller; Nicholas C. ;   et al. | 2011-05-26 |
Mixed lithography with dual resist and a single pattern transfer Grant 7,914,970 - Fuller , et al. March 29, 2 | 2011-03-29 |
Method and process for forming a self-aligned silicide contact Grant 7,544,610 - Cabral, Jr. , et al. June 9, 2 | 2009-06-09 |
Mixed Lithography With Dual Resist And A Single Pattern Transfer App 20090092799 - Fuller; Nicholas C. ;   et al. | 2009-04-09 |
Selective silicide formation by electrodeposit displacement reaction Grant 7,501,345 - Basker , et al. March 10, 2 | 2009-03-10 |
Method And Process For Forming A Self-aligned Silicide Contact App 20080274611 - Cabral; Cyril ;   et al. | 2008-11-06 |
Method and process for forming a self-aligned silicide contact App 20060051961 - Cabral; Cyril JR. ;   et al. | 2006-03-09 |
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