Prall; Kirk

Patent Applications and Registrations

Patent applications and USPTO patent grants for Prall; Kirk.The latest application filed is for "memory cell imprint avoidance".

Company Profile

3.52.37

Prall; Kirk - Boise ID
Prall; Kirk - Bosie ID
PRALL, KIRK - US

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Memory Cell Imprint Avoidance App 20210280231 - Calderoni; Alessandro ; et al.	2021-09-09
Memory cell imprint avoidance Grant 10,978,128 - Calderoni , et al. April 13, 2	2021-04-13
Memory Cell Imprint Avoidance App 20200090728 - Calderoni; Alessandro ; et al.	2020-03-19
Memory cell imprint avoidance Grant 10,475,500 - Calderoni , et al. Nov	2019-11-12
Memory Cell Imprint Avoidance App 20180366176 - Calderoni; Alessandro ; et al.	2018-12-20
Memory cell imprint avoidance Grant 10,083,732 - Calderoni , et al. September 25, 2	2018-09-25
Memory Cell Imprint Avoidance App 20170365323 - Calderoni; Alessandro ; et al.	2017-12-21
Memory cell imprint avoidance Grant 9,721,639 - Calderoni , et al. August 1, 2	2017-08-01
Structure and method of fabricating a transistor having a trench gate Grant 8,647,949 - Smith , et al. February 11, 2	2014-02-11
Memory Devices And Methods Of Forming Memory Devices App 20120132979 - Prall; Kirk ; et al.	2012-05-31
Structure And Method Of Fabricating A Transistor Having A Trench Gate App 20110124178 - Smith; Michael ; et al.	2011-05-26
Multi-state memory cell with asymmetric charge trapping Grant 7,911,837 - Prall March 22, 2	2011-03-22
Structure and method of fabricating a transistor having a trench gate Grant 7,879,665 - Smith , et al. February 1, 2	2011-02-01
Method of Forming Memory Devices by Performing Halogen Ion Implantation and Diffusion Processes App 20110013463 - Prall; Kirk ; et al.	2011-01-20
Method of forming memory devices by performing halogen ion implantation and diffusion processes Grant 7,824,994 - Prall , et al. November 2, 2	2010-11-02
Contactless uniform-tunneling separate p-well (CUSP) non-volatile memory array architecture, fabrication and operation Grant 7,696,557 - Chen , et al. April 13, 2	2010-04-13
Multi-state Memory Cell With Asymmetric Charge Trapping App 20100039869 - Prall; Kirk	2010-02-18
Multi-state memory cell with asymmetric charge trapping Grant 7,616,482 - Prall November 10, 2	2009-11-10
Multi-state memory cell with asymmetric charge trapping Grant 7,577,027 - Prall August 18, 2	2009-08-18
Method for forming a floating gate memory with polysilicon local interconnects Grant 7,569,468 - Chen , et al. August 4, 2	2009-08-04
Method for forming an array with polysilicon local interconnects Grant 7,517,749 - Chen , et al. April 14, 2	2009-04-14
Method of Forming Memory Devices by Performing Halogen Ion Implantation and Diffusion Processes App 20090068812 - Prall; Kirk ; et al.	2009-03-12
Method of forming memory devices by performing halogen ion implantation and diffusion processes Grant 7,485,528 - Prall , et al. February 3, 2	2009-02-03
Structure And Method Of Fabricating A Transistor Having A Trench Gate App 20080200005 - Smith; Michael ; et al.	2008-08-21
Structure and method of fabricating a transistor having a trench gate Grant 7,332,419 - Smith , et al. February 19, 2	2008-02-19
Method Of Forming Memory Devices By Performing Halogen Ion Implantation And Diffusion Processes App 20080014698 - Prall; Kirk ; et al.	2008-01-17
Structure and method of fabricating a transistor having a trench gate Grant 7,279,710 - Smith , et al. October 9, 2	2007-10-09
Contactless uniform-tunneling separate p-well (cusp)non-volatile memory array architecture, fabrication and operation App 20070164348 - Chen; Chun ; et al.	2007-07-19
Contactless uniform-tunneling separate P-well (CUSP) non-volatile memory array architecture, fabrication and operation Grant 7,199,422 - Chen , et al. April 3, 2	2007-04-03
Method for forming polysilicon local interconnects Grant 7,115,509 - Chen , et al. October 3, 2	2006-10-03
Multi-state memory cell with asymmetric charge trapping App 20060203555 - Prall; Kirk	2006-09-14
Multi-state memory cell with asymmetric charge trapping App 20060203554 - Prall; Kirk	2006-09-14
Multi-state memory cell with asymmetric charge trapping Grant 7,072,217 - Prall July 4, 2	2006-07-04
Fabricating a 2F.sup.2 memory device with a horizontal floating gate Grant 6,998,314 - Prall February 14, 2	2006-02-14
Structure and method of fabricating a transistor having a trench gate App 20060011948 - Smith; Michael ; et al.	2006-01-19
Method for forming a floating gate memory with polysilicon local interconnects App 20060008987 - Chen; Chun ; et al.	2006-01-12
Method for forming an array with polysilicon local interconnects App 20060008989 - Chen; Chun ; et al.	2006-01-12
Method of forming a memory cell App 20060008988 - Chen; Chun ; et al.	2006-01-12
Method for forming polysilicon local interconnects App 20060008963 - Chen; Chun ; et al.	2006-01-12
Method for forming polysilicon local interconnects App 20060009035 - Chen; Chun ; et al.	2006-01-12
Memory cell with polysilicon local interconnects App 20060006455 - Chen; Chun ; et al.	2006-01-12
Contactless uniform-tunneling separate p-well (cusp) non-volatile memory array architecture, fabrication and operation Grant 6,984,547 - Chen , et al. January 10, 2	2006-01-10
Memory with polysilicon local interconnects App 20050285148 - Chen, Chun ; et al.	2005-12-29
Structure and method of fabricating a transistor having a trench gate Grant 6,949,795 - Smith , et al. September 27, 2	2005-09-27
Multi-state memory cell with asymmetric charge trapping App 20050185466 - Prall, Kirk	2005-08-25
Contactless uniform-tunneling separate p-well (CUSP) non-volatile memory array architecture, fabrication and operation Grant 6,930,350 - Chen , et al. August 16, 2	2005-08-16
Structure and method of fabricating a transistor having a trench gate App 20050124118 - Smith, Michael ; et al.	2005-06-09
Method for forming polysilicon local interconnects App 20050104114 - Chen, Chun ; et al.	2005-05-19
Structure and method of fabricating a transistor having a trench gate App 20050104122 - Smith, Michael ; et al.	2005-05-19
Contactless uniform-tunneling separate P-well (CUSP) non-volatile memory array architecture, fabrication and operation App 20050099846 - Chen, Chun ; et al.	2005-05-12
Integrated circuit having self-aligned CVD-tungsten/titanium contact plugs strapped with metal interconnect and method of manufacture Grant 6,812,512 - Prall , et al. November 2, 2	2004-11-02
2F2 memory device App 20040141359 - Prall, Kirk	2004-07-22
2F2 memory device system Grant 6,759,707 - Prall July 6, 2	2004-07-06
Contactless uniform-tunneling separate p-well (cusp) non-volatile memory array architecture, fabrication and operation App 20040072391 - Chen, Chun ; et al.	2004-04-15
Contactless uniform-tunneling separate p-well (CUSP) non-volatile memory array architecture, fabrication and operation App 20040071008 - Chen, Chun ; et al.	2004-04-15
Integrated circuit having self-aligned CVD-tungsten/titanium contact plugs strapped with metal interconnect and method of manufacture Grant 6,686,288 - Prall , et al. February 3, 2	2004-02-03
Contactless uniform-tunneling separate p-well (CUSP) non-volatile memory array architecture, fabrication and operation Grant 6,649,453 - Chen , et al. November 18, 2	2003-11-18
Reduced pitch laser redundancy fuse bank structure Grant 6,597,054 - Prall , et al. July 22, 2	2003-07-22
2F2 memory device system and method App 20020127798 - Prall, Kirk	2002-09-12
Contact Plug App 20020093099 - JUENGLING, WERNER ; et al.	2002-07-18
Method Of Forming A Semiconductor-on-insulator Transistor App 20020048883 - PRALL, KIRK	2002-04-25
Semiconductor processing method of fabricating field effect transistors Grant 6,326,250 - Ahmad , et al. December 4, 2	2001-12-04
Reduced leakage DRAM storage unit App 20010040816 - Wu, Zhigiang (Jeff) ; et al.	2001-11-15
Method for forming a semiconductor connection with a top surface having an enlarged recess App 20010039113 - Blalock, Guy ; et al.	2001-11-08
Integrated circuit having self-aligned CVD-tungsten/titanium contact plugs strapped with metal interconnect and method of manufacture App 20010019893 - Prall, Kirk ; et al.	2001-09-06
Method of forming titanium silicide and titanium by chemical vapor deposition and resulting apparatus App 20010006240 - Doan, Trung T. ; et al.	2001-07-05
Methods of forming a contact having titanium silicide and titanium formed by chemical vapor deposition Grant 6,255,216 - Doan , et al. July 3, 2	2001-07-03
Ion implantation with programmable energy, angle, and beam current Grant 6,229,148 - Prall , et al. May 8, 2	2001-05-08
Apparatus having titanium silicide and titanium formed by chemical vapor deposition Grant 6,208,033 - Doan , et al. March 27, 2	2001-03-27
Reduced leakage DRAM storage unit Grant 6,157,566 - Wu , et al. December 5, 2	2000-12-05
Semiconductor processing method of forming a conductively doped semiconductive material plug within a contact opening Grant 6,067,680 - Pan , et al. May 30, 2	2000-05-30
Method for forming a semiconductor connection with a top surface having an enlarged recess Grant 6,066,559 - Gonzalez , et al. May 23, 2	2000-05-23
Method for forming a semiconductor connection with a top surface having an enlarged recess Grant 6,043,151 - Gonzalez , et al. March 28, 2	2000-03-28
Integrated circuit having self-aligned CVD-tungsten/titanium contact plugs strapped with metal interconnect and method of manufacture Grant 5,990,021 - Prall , et al. November 23, 1	1999-11-23
Method of forming titanium silicide and titanium by chemical vapor deposition Grant 5,976,976 - Doan , et al. November 2, 1	1999-11-02
Method for cleaning waste matter from the backside of a semiconductor wafer substrate Grant 5,958,796 - Prall , et al. September 28, 1	1999-09-28
Semiconductor-on-insulator transistor and memory circuitry employing semiconductor-on-insulator transistors Grant 5,929,476 - Prall July 27, 1	1999-07-27
Method of forming contact plugs Grant 5,858,865 - Juengling , et al. January 12, 1	1999-01-12
Semiconductor processing method of fabricating field effect transistors Grant 5,849,615 - Ahmad , et al. December 15, 1	1998-12-15
Field effect transistors comprising electrically conductive plugs having monocrystalline and polycrystalline silicon Grant 5,831,334 - Prall , et al. November 3, 1	1998-11-03
Method of forming a resistor and integrated circuitry having a resistor construction Grant 5,821,150 - Prall , et al. October 13, 1	1998-10-13
Acceleration of etch selectivity for self-aligned contact Grant 5,804,506 - Haller , et al. September 8, 1	1998-09-08
Reduced pitch laser redundancy fuse bank structure Grant 5,747,869 - Prall , et al. May 5, 1	1998-05-05
High performance PMOSFET using split-polysilicon CMOS process incorporating advanced stacked capacitior cells for fabricating multi-megabit DRAMS Grant 5,716,862 - Ahmad , et al. February 10, 1	1998-02-10
Field effect transistor Grant 5,677,573 - Prall , et al. October 14, 1	1997-10-14
Method of forming field effect transistors relative to a semiconductor substrate and field effect transistors produced according to the method Grant 5,597,746 - Prall January 28, 1	1997-01-28
Array of non-volatile sonos memory cells Grant 5,424,569 - Prall June 13, 1	1995-06-13
Method of forming an array of non-volatile sonos memory cells and array of non-violatile sonos memory cells Grant 5,387,534 - Prall February 7, 1	1995-02-07