| Patent | Date |
|---|
Integrated circuits with alignment marks and methods of producing the same
Grant 9,633,882 - Yu , et al. April 25, 2 | 2017-04-25 |
Integrated Circuits With Alignment Marks And Methods Of Producing The Same
App 20170092523 - Yu; Ying ; et al. | 2017-03-30 |
Critical dimension for trench and vias
Grant 8,293,545 - Cong , et al. October 23, 2 | 2012-10-23 |
Critical Dimension For Trench And Vias
App 20090108257 - Cong; Hai ; et al. | 2009-04-30 |
Method of making direct contact on gate by using dielectric stop layer
App 20050136573 - Rajverma, Purakh ; et al. | 2005-06-23 |
Method of forming an inductor with continuous metal deposition
App 20050124131 - Hweing, Chit ; et al. | 2005-06-09 |
Method of forming an inductor with continuous metal deposition
Grant 6,852,605 - Ng , et al. February 8, 2 | 2005-02-08 |
Method of blocking nitrogen from thick gate oxide during dual gate CMP
Grant 6,821,904 - Pradeep , et al. November 23, 2 | 2004-11-23 |
Method of forming an inductor with continuous metal deposition
App 20040217440 - Ng, Chit Hwei ; et al. | 2004-11-04 |
Image compensation device for a scanning electron microscope
Grant 6,791,083 - Peng , et al. September 14, 2 | 2004-09-14 |
Linear polishing for improving substrate uniformity
Grant 6,726,545 - Balakumar , et al. April 27, 2 | 2004-04-27 |
Method of forming a surface coating layer within an opening within a body by atomic layer deposition
Grant 6,716,693 - Chan , et al. April 6, 2 | 2004-04-06 |
Method for forming variable-K gate dielectric
Grant 6,709,934 - Lee , et al. March 23, 2 | 2004-03-23 |
Method of blocking nitrogen from thick gate oxide during dual gate CMP
App 20040023506 - Pradeep, Yelehanka Ramachandramurthy ; et al. | 2004-02-05 |
Image compensation device for a scanning electron microscope
App 20040016881 - Peng, Kevin Chan Ee ; et al. | 2004-01-29 |
Method to form both high and low-k materials over the same dielectric region, and their application in mixed mode circuits
App 20040004054 - Pradeep, Yelehanka Ramachandramurthy ; et al. | 2004-01-08 |
Toxic residual gas removal by non-reactive ion sputtering
Grant 6,660,642 - Zheng , et al. December 9, 2 | 2003-12-09 |
Linear polishing for improving substrate uniformity
App 20030203710 - Balakumar, Subramanian ; et al. | 2003-10-30 |
Method to form elevated source/drain using poly spacer
Grant 6,566,208 - Pan , et al. May 20, 2 | 2003-05-20 |
Method to form a self-aligned CMOS inverter using vertical device integration
App 20030075758 - Sundaresan, Ravi ; et al. | 2003-04-24 |
Toxic residual gas removal by non-reactive ion sputtering
App 20030022504 - Zheng, Zou ; et al. | 2003-01-30 |
Method to improve latchup by forming selective sloped staircase STI structure to use in the I/0 or latchup sensitive area
App 20030017710 - Yang, Pan ; et al. | 2003-01-23 |
Method for forming variable-K gate dielectric
App 20020173106 - Lee, James Yong Meng ; et al. | 2002-11-21 |
Method to form an air-gap under the edges of a gate electrode by using disposable spacer/liner
Grant 6,468,877 - Pradeep , et al. October 22, 2 | 2002-10-22 |
Method of fabricating a shallow trench isolation structure with reduced local oxide recess near corner
Grant 6,468,853 - Balasubramanian , et al. October 22, 2 | 2002-10-22 |
Method to form a self-aligned CMOS inverter using vertical device integration
Grant 6,461,900 - Sundaresan , et al. October 8, 2 | 2002-10-08 |
Method to control the channel length of a vertical transistor by first forming channel using selective epi and source/drain using implantation
Grant 6,436,770 - Leung , et al. August 20, 2 | 2002-08-20 |
Method to form a vertical transistor by selective epitaxial growth and delta doped silicon layers
App 20020102784 - Lee, James Yong Meng ; et al. | 2002-08-01 |
Method For Fabricating A Self Aligned S/d Cmos Device On Insulated Layer By Forming A Trench Along The Sti And Fill With Oxide
App 20020102798 - Zheng, Jia Zhen ; et al. | 2002-08-01 |
Method for forming variable-K gate dielectric
App 20020100947 - Lee, James Yong Meng ; et al. | 2002-08-01 |
Method to form very high mobility vertical channel transistor by selective deposition of SiGe or multi-quantum wells (MQWs)
App 20020098655 - Zheng, Jia Zhen ; et al. | 2002-07-25 |
Method for fabricating a self aligned S/D CMOS device on insulated layer by forming a trench along the STI and fill with oxide
Grant 6,417,054 - Zheng , et al. July 9, 2 | 2002-07-09 |
Method to form low-overlap-capacitance transistors by forming microtrench at the gate edge
Grant 6,417,056 - Quek , et al. July 9, 2 | 2002-07-09 |
Method to form self-aligned, L-shaped sidewall spacers
App 20020076877 - Gupta, Subhash ; et al. | 2002-06-20 |
Method to form a low parasitic capacitance pseudo-SOI CMOS device
Grant 6,403,485 - Quek , et al. June 11, 2 | 2002-06-11 |
Method for forming dual gate oxide
Grant 6,399,448 - Mukhopadhyay , et al. June 4, 2 | 2002-06-04 |
Method for forming an extended metal gate using a damascene process
Grant 6,387,765 - Chhagan , et al. May 14, 2 | 2002-05-14 |
Method to form a recessed source drain on a trench side wall with a replacement gate technique
Grant 6,380,088 - Chan , et al. April 30, 2 | 2002-04-30 |
Method for forming an L-shaped spacer using a disposable polysilicon spacer
Grant 6,346,468 - Pradeep , et al. February 12, 2 | 2002-02-12 |
Self aligned T-top gate process integration
Grant 6,337,262 - Pradeep , et al. January 8, 2 | 2002-01-08 |
Method to fabricate a floating gate with a sloping sidewall for a flash memory
App 20020000604 - Chhagan, Vijai Komar N. ; et al. | 2002-01-03 |
Method of forming spacers of multiple widths
Grant 6,316,304 - Pradeep , et al. November 13, 2 | 2001-11-13 |
Method to form a balloon shaped STI using a micro machining technique to remove heavily doped silicon
Grant 6,313,008 - Leung , et al. November 6, 2 | 2001-11-06 |
Method to form smaller channel with CMOS device by isotropic etching of the gate materials
Grant 6,306,715 - Chan , et al. October 23, 2 | 2001-10-23 |
Method for forming an extended metal gate using a damascene process
Grant 6,303,447 - Chhagan , et al. October 16, 2 | 2001-10-16 |
Method to form transistors with multiple threshold voltages (VT) using a combination of different work function gate materials
Grant 6,300,177 - Sundaresan , et al. October 9, 2 | 2001-10-09 |
Method for forming an L-shaped spacer with a disposable organic top coating
Grant 6,294,480 - Pradeep , et al. September 25, 2 | 2001-09-25 |
Method for forming a T-gate for better salicidation
Grant 6,284,613 - Subrahmanyam , et al. September 4, 2 | 2001-09-04 |
Method to reduce trench cone formation in the fabrication of shallow trench isolations
Grant 6,281,093 - Pradeep , et al. August 28, 2 | 2001-08-28 |
Method of forming a sidewall spacer and a salicide blocking shape, using only one silicon nitride layer
Grant 6,277,683 - Pradeep , et al. August 21, 2 | 2001-08-21 |
High selective nitride spacer etch with high ratio of spacer width to deposited nitride thickness
Grant 6,277,700 - Yu , et al. August 21, 2 | 2001-08-21 |
Method to form an L-shaped silicon nitride sidewall spacer
Grant 6,251,764 - Pradeep , et al. June 26, 2 | 2001-06-26 |
Method to form self-sealing air gaps between metal interconnects
Grant 6,228,770 - Pradeep , et al. May 8, 2 | 2001-05-08 |
Method for forming high-density high-capacity capacitor
Grant 6,211,008 - Yu , et al. April 3, 2 | 2001-04-03 |
Method for forming a lightly doped source and drain structure using an L-shaped spacer
Grant 6,156,598 - Zhou , et al. December 5, 2 | 2000-12-05 |
Method for a lightly doped drain structure
Grant 5,858,847 - Zhou , et al. January 12, 1 | 1999-01-12 |
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