loadpatents
name:-0.003835916519165
name:-0.014718055725098
name:-0.00044608116149902
Prabhu; Ashok Narayan Patent Filings

Prabhu; Ashok Narayan

Patent Applications and Registrations

Patent applications and USPTO patent grants for Prabhu; Ashok Narayan.The latest application filed is for "low temperature co-fired ceramic-metal packaging technology".

Company Profile
0.14.1
  • Prabhu; Ashok Narayan - East Windsor NJ
  • Prabhu; Ashok Narayan - East Windson NJ
  • Prabhu; Ashok Narayan - Mercer NJ
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Low temperature co-fired ceramic-metal packaging technology
Grant 6,713,862 - Palanisamy , et al. March 30, 2
2004-03-30
Method for the reduction of lateral shrinkage in multilayer circuit boards on a substrate
Grant 6,709,749 - Kumar , et al. March 23, 2
2004-03-23
Low temperature co-fired ceramic-metal packaging technology
App 20030034564 - Palanisamy, Ponnusamy ;   et al.
2003-02-20
Integrated heat sinking packages using low temperature co-fired ceramic metal circuit board technology
Grant 6,455,930 - Palanisamy , et al. September 24, 2
2002-09-24
Method for fabricating double sided ceramic circuit boards using a titanium support substrate
Grant 6,286,204 - Sreeram , et al. September 11, 2
2001-09-11
Back panel for a plasma display device
Grant 6,168,490 - Hozer , et al. January 2, 2
2001-01-02
Low dielectric loss glasses
Grant 6,017,642 - Kumar , et al. January 25, 2
2000-01-25
Miniature power supply
Grant 6,011,330 - Goodman , et al. January 4, 2
2000-01-04
Low dielectric loss glass ceramic compositions
Grant 5,958,807 - Kumar , et al. September 28, 1
1999-09-28
Multilayer ceramic circuit boards including embedded capacitors
Grant 5,953,203 - Tormey , et al. September 14, 1
1999-09-14
Mounting structure for a tessellated electronic display having a multilayer ceramic structure and tessellated electronic display
Grant 5,880,705 - Onyskevych , et al. March 9, 1
1999-03-09
Method for the reduction of lateral shrinkage in multilayer circuit boards on a substrate
Grant 5,876,536 - Kumar , et al. March 2, 1
1999-03-02
Method to control cavity dimensions of fired multilayer circuit boards on a support
Grant 5,858,145 - Sreeram , et al. January 12, 1
1999-01-12
Electronic circuit chip package
Grant 5,847,935 - Thaler , et al. December 8, 1
1998-12-08
Tessellated electroluminescent display having a multilayer ceramic substrate
Grant 5,644,327 - Onyskevych , et al. July 1, 1
1997-07-01

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