Power Intergrations, Inc.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Power Intergrations, Inc..The latest application filed is for "method of fabricating a high-voltage transistor with an extended drain structure".

Company Profile

0.13.1

Power Intergrations, Inc. - San Jose CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Magnetically coupled galvanically isolated communication using lead frame Grant 10,079,543 - Balakrishnan , et al. September 18, 2	2018-09-18
PFC shutdown circuit for light load Grant 9,866,108 - Mayell , et al. January 9, 2	2018-01-09
Indirect regulation of output current in power converter Grant 9,621,019 - Zhang , et al. April 11, 2	2017-04-11
Method and apparatus for implementing a power converter input terminal voltage discharge circuit Grant 9,065,340 - Balakrishnan , et al. June 23, 2	2015-06-23
Method and apparatus to control a power factor correction circuit Grant 8,487,601 - Saint-Pierre July 16, 2	2013-07-16
Leakage compensation for sample and hold devices Grant 8,179,166 - Wang May 15, 2	2012-05-15
Temperature independent reference circuit Grant 7,999,606 - Kung , et al. August 16, 2	2011-08-16
Method and apparatus to control a power supply for high efficiency Grant 7,696,737 - Polivka April 13, 2	2010-04-13
Method and apparatus for increasing the power capability of a power supply Grant 7,593,242 - Park , et al. September 22, 2	2009-09-22
Method and apparatus for reducing audio noise in a switching regulator Grant 7,521,908 - Balakrishnan , et al. April 21, 2	2009-04-21
Method of fabricating a high-voltage transistor with an extended drain structure App 20070293002 - Disney; Donald Ray	2007-12-20
High-voltage lateral transistor with a multi-layered extended drain structure Grant 6,815,293 - Disney , et al. November 9, 2	2004-11-09
Method and apparatus for fault condition protection of a switched mode power supply Grant 6,788,514 - Balakrishnan September 7, 2	2004-09-07
Method of fabricating a high-voltage transistor with a multi-layered extended drain structure Grant 6,635,544 - Disney October 21, 2	2003-10-21

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.