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Built-in self-test arrangement for integrated circuit memory devices
Grant 7,328,388 - Hii , et al. February 5, 2 | 2008-02-05 |
Built-in self-test arrangement for integrated circuit memory devices
Grant 7,278,078 - Hii , et al. October 2, 2 | 2007-10-02 |
Built-in self-test arrangement for integrated circuit memory devices
App 20060242521 - Hii; Kuong Hua ; et al. | 2006-10-26 |
Method to test memories that operate at twice their nominal bandwidth
App 20050144525 - Heragu, Keerthinarayan ; et al. | 2005-06-30 |
Built-in self-test arrangement for integrated circuit memory devices
App 20050022084 - Hii, Kuong Hua ; et al. | 2005-01-27 |
Built-in self-test arrangement for integrated circuit memory devices
Grant 6,801,461 - Hii , et al. October 5, 2 | 2004-10-05 |
Built-in self-test arrangement for integrated circuit memory devices
App 20020089887 - Hii, Kuong Hua ; et al. | 2002-07-11 |
Built-in self-test arrangement for integrated circuit memory devices
App 20020071325 - Hii, Kuong Hua ; et al. | 2002-06-13 |
Data invert jump instruction test for built-in self-test
Grant 5,953,272 - Powell , et al. September 14, 1 | 1999-09-14 |
Apparatus and method for subarray testing in dynamic random access memories using a built-in-self-test unit
Grant 5,923,599 - Hii , et al. July 13, 1 | 1999-07-13 |
Built-in self-test arrangement for integrated circuit memory devices
Grant 5,883,843 - Hii , et al. March 16, 1 | 1999-03-16 |
Internal/external clock option for built-in self test
Grant 5,875,153 - Hii , et al. February 23, 1 | 1999-02-23 |
System and method for structurally testing integrated circuit devices
Grant 5,694,402 - Butler , et al. December 2, 1 | 1997-12-02 |
Test circuit and scan tested logic device with isolated data lines during testing
Grant 5,032,783 - Hwang , et al. July 16, 1 | 1991-07-16 |
Distributed pseudo random sequence control with universal polynomial function generator for LSI/VLSI test systems
Grant 4,870,346 - Mydill , et al. September 26, 1 | 1989-09-26 |
Parallel/serial scan system for testing logic circuits
Grant 4,710,933 - Powell , et al. December 1, 1 | 1987-12-01 |
Partitioned scan-testing system
Grant 4,710,931 - Bellay , et al. December 1, 1 | 1987-12-01 |
Modularized scan path for serially tested logic circuit
Grant 4,701,921 - Powell , et al. October 20, 1 | 1987-10-20 |
Transparent shift register latch for isolating peripheral ports during scan testing of a logic circuit
Grant 4,698,588 - Hwang , et al. October 6, 1 | 1987-10-06 |
Architecture and method for testing VLSI processors
Grant 4,597,080 - Thatte , et al. June 24, 1 | 1986-06-24 |
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