Poteet; Kenneth A.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Poteet; Kenneth A..The latest application filed is for "high-speed memory arranged for operating synchronously with a microprocessor".

Company Profile

0.15.0

Poteet; Kenneth A. - Houston TX
Poteet; Kenneth A. - Sugar Land TX
Poteet; Kenneth A. - San Jose CA
Poteet; Kenneth A. - Sugarland TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
High-speed memory arranged for operating synchronously with a microprocessor Grant 6,088,280 - Vogley , et al. July 11, 2	2000-07-11
Random access memory with latency arranged for operating synchronously with a micro processor and a system including a data processor, a synchronous DRAM, a peripheral device, and a system clock Grant 5,808,958 - Vogley , et al. September 15, 1	1998-09-15
Apparatus and method for a memory unit with a processor integrated therein Grant 5,678,021 - Pawate , et al. October 14, 1	1997-10-14
Reduced area word line driving circuit for random access memory Grant 5,633,832 - Patel , et al. May 27, 1	1997-05-27
Burst random access memory employing sequenced banks of local tri-state drivers Grant 5,617,555 - Patel , et al. April 1, 1	1997-04-01
Random access memory arranged for operating synchronously with a microprocessor and a system including a data processor, a synchronous DRAM, a peripheral device, and a system clock Grant 5,587,954 - Vogley , et al. December 24, 1	1996-12-24
Timing control circuit for synchronous static random access memory Grant 5,559,752 - Stephens, Jr. , et al. September 24, 1	1996-09-24
Dual-port random access memory having reduced architecture Grant 5,535,172 - Reddy , et al. July 9, 1	1996-07-09
Process of making and a DRAM standby charge pump with oscillator having fuse selectable frequencies Grant 5,410,510 - Smith , et al. April 25, 1	1995-04-25
Fuse selectable timing signals for internal signal generators Grant 5,402,390 - Ho , et al. March 28, 1	1995-03-28
System including a data processor, a synchronous dram, a peripheral device, and a system clock Grant 5,390,149 - Vogley , et al. February 14, 1	1995-02-14
Method and apparatus for implementing .times.2 parity DRAM for 16 bit systems from .times.4 parity DRAM Grant 5,287,311 - Tso , et al. February 15, 1	1994-02-15
Memory module arranged for data and parity bits Grant 5,228,132 - Neal , et al. July 13, 1	1993-07-13
Memory module arranged for data and parity bits Grant 5,089,993 - Neal , et al. February 18, 1	1992-02-18
Detector and integrated circuit device including charge pump circuits for high load conditions Grant 5,075,572 - Poteet , et al. December 24, 1	1991-12-24

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