loadpatents
name:-0.72017812728882
name:-0.066765069961548
name:-0.0042510032653809
Potash; Hanan Patent Filings

Potash; Hanan

Patent Applications and Registrations

Patent applications and USPTO patent grants for Potash; Hanan.The latest application filed is for "enhanced security computer processor with mentor circuits".

Company Profile
6.40.24
  • Potash; Hanan - Austin TX
  • Potash; Hanan - La Jolla CA
  • Potash; Hanan - Canoga Park CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Computing device with resource manager and civilware tier
Grant 11,093,286 - Potash August 17, 2
2021-08-17
Electronic computer-aided design tool
Grant 11,062,068 - Potash July 13, 2
2021-07-13
Enhanced Security Computer Processor With Mentor Circuits
App 20210103443 - Potash; Hanan
2021-04-08
Enhanced security computer processor with mentor circuits
Grant 10,810,010 - Potash October 20, 2
2020-10-20
Enhanced Security Computer Processor With Mentor Circuits
App 20190179634 - Potash; Hanan
2019-06-13
Computer processor with operand/variable-mapped namespace
Grant 10,140,122 - Potash Nov
2018-11-27
Electronic Computer-aided Design Tool
App 20180336303 - Potash; Hanan
2018-11-22
Processor with frames/bins structure in local high speed memory
Grant 10,095,641 - Potash October 9, 2
2018-10-09
Processor with logical mentor
Grant 10,067,878 - Potash September 4, 2
2018-09-04
Computing device with frames/bins structure, mentor layer and plural operand processing
Grant 10,061,511 - Potash August 28, 2
2018-08-28
Electronic computer-aided design tool
Grant 9,984,186 - Potash May 29, 2
2018-05-29
Processor that uses plural form information
Grant 9,977,693 - Potash May 22, 2
2018-05-22
Computing Device With Resource Manager And Civilware Tier
App 20170308405 - Potash; Hanan
2017-10-26
Electronic Computer-aided Design Tool
App 20170242944 - Potash; Hanan
2017-08-24
Processor With Frames/bins Structure In Local High Speed Memory
App 20170083464 - Potash; Hanan
2017-03-23
Processor With Logical Mentor
App 20170083449 - Potash; Hanan
2017-03-23
Computing Device With Frames/bins Structure, Mentor Layer And Plural Operand Processing
App 20170083237 - Potash; Hanan
2017-03-23
Computer Processor With Operand/variable-mapped Namespace
App 20170083434 - Potash; Hanan
2017-03-23
Processor That Uses Plural Form Information
App 20170083238 - Potash; Hanan
2017-03-23
Frame handler for high-speed fiber optic communication interface
App 20020154647 - Potash, Hanan
2002-10-24
Efficient method and system for the installation of data conduit in pre-existing structures
App 20020114595 - Potash, Hanan
2002-08-22
Efficient mechanism for inter-thread communication within a multi-threaded computer system
App 20020103847 - Potash, Hanan
2002-08-01
Programmed load precession machine
App 20020103990 - Potash, Hanan
2002-08-01
Matrices with memories
Grant 6,340,588 - Nova , et al. January 22, 2
2002-01-22
Automated sorting system for matrices with memory
Grant 6,329,139 - Nova , et al. December 11, 2
2001-12-11
Method for tagging and screening molecules
Grant 6,319,668 - Nova , et al. November 20, 2
2001-11-20
Solid support matrices with memories and combinatorial libraries therefrom
Grant 6,284,459 - Nova , et al. September 4, 2
2001-09-04
Matrices with memories and uses thereof
Grant 6,100,026 - Nova , et al. August 8, 2
2000-08-08
Matrices with memories and uses thereof
Grant 6,017,496 - Nova , et al. January 25, 2
2000-01-25
Matrices with memories and uses thereof
Grant 5,961,923 - Nova , et al. October 5, 1
1999-10-05
Electrically alterable resistive component stacked above a semiconductor substrate
Grant 5,296,722 - Potash , et al. March 22, 1
1994-03-22
Digital computer having an interconnect mechanism stacked above a semiconductor substrate
Grant 5,148,256 - Potash , et al. * September 15, 1
1992-09-15
Digital computer having control and arithmetic sections stacked above semiconductor substrate
Grant 4,933,735 - Potash , et al. * June 12, 1
1990-06-12
Linking scalar results directly to scalar operation inputs on a bidirectional databus in a computer which superpositions vector and scalar operations
Grant 4,837,730 - Cook , et al. June 6, 1
1989-06-06
Backplane structure for a computer superpositioning scalar and vector operations
Grant 4,777,615 - Potash October 11, 1
1988-10-11
Bi-directional databus system for supporting superposition of vector and scalar operations in a computer
Grant 4,760,518 - Potash , et al. July 26, 1
1988-07-26
Method of operating a bus in a data processing system via a repetitive three stage signal sequence
Grant 4,744,024 - Potash , et al. May 10, 1
1988-05-10
Address translation buffer
Grant 4,538,241 - Levin , et al. August 27, 1
1985-08-27
Flexible computer architecture using arrays of standardized microprocessors customized for pipeline and parallel operations
Grant 4,467,409 - Potash , et al. August 21, 1
1984-08-21
Method of transforming high level language statements into multiple lower level language instruction sets
Grant 4,463,423 - Potash , et al. July 31, 1
1984-07-31
Branch predicting computer
Grant 4,435,756 - Potash March 6, 1
1984-03-06
Digital device for time-multiplexing multiple tasks
Grant 4,393,465 - Potash July 12, 1
1983-07-12
Digital computer having programmable structure
Grant 4,346,438 - Potash , et al. August 24, 1
1982-08-24
Digital device with interconnect matrix
Grant 4,327,355 - Genter , et al. April 27, 1
1982-04-27
Peak Detection System
Grant 3,668,532 - Potash June 6, 1
1972-06-06

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