loadpatents
name:-0.047173023223877
name:-0.0192711353302
name:-0.0011501312255859
Post; Ian R. Patent Filings

Post; Ian R.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Post; Ian R..The latest application filed is for "penetrating implant for forming a semiconductor device".

Company Profile
0.17.15
  • Post; Ian R. - Portland OR
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Penetrating implant for forming a semiconductor device
Grant 8,741,720 - Curello , et al. June 3, 2
2014-06-03
Penetrating Implant For Forming A Semiconductor Device
App 20130224926 - Curello; Giuseppe ;   et al.
2013-08-29
Penetrating implant for forming a semiconductor device
Grant 8,426,927 - Curello , et al. April 23, 2
2013-04-23
Selective spacer formation on transistors of different classes on the same device
Grant 8,174,060 - Curello , et al. May 8, 2
2012-05-08
Selective spacer formation on transistors of different classes on the same device
Grant 8,154,067 - Curello , et al. April 10, 2
2012-04-10
Penetrating Implant For Forming A Semiconductor Device
App 20110215422 - Curello; Giuseppe ;   et al.
2011-09-08
Selective Spacer Formation On Transistors Of Different Classes On The Same Device
App 20110157854 - Curello; Giuseppe ;   et al.
2011-06-30
Penetrating implant for forming a semiconductor device
Grant 7,943,468 - Curello , et al. May 17, 2
2011-05-17
Penetrating Implant For Forming A Semiconductor Device
App 20090242998 - Curello; Giuseppe ;   et al.
2009-10-01
Selective Spacer Formation On Transistors Of Different Classes On The Same Device
App 20090189193 - CURELLO; GIUSEPPE ;   et al.
2009-07-30
Active region spacer for semiconductor devices and method to form the same
Grant 7,560,780 - Curello , et al. July 14, 2
2009-07-14
Selective spacer formation on transistors of different classes on the same device
Grant 7,541,239 - Curello , et al. June 2, 2
2009-06-02
Selective spacer formation on transistors of different classes on the same device
App 20080003746 - Curello; Giuseppe ;   et al.
2008-01-03
Active region spacer for semiconductor devices and method to form the same
App 20070132057 - Curello; Giuseppe ;   et al.
2007-06-14
Indium-boron dual halo MOSFET
Grant 7,226,843 - Weber , et al. June 5, 2
2007-06-05
Method of fabricating MOSFET transistors with multiple threshold voltages by halo compensation and masks
Grant 6,979,609 - Post , et al. December 27, 2
2005-12-27
Method of fabricating dual threshold voltage n-channel and p-channel mosfets with a single extra masked implant operation
Grant 6,803,285 - Mistry , et al. October 12, 2
2004-10-12
Method of fabricating MOSFET transistors with multiple threshold voltages by halo compensation and masks
Grant 6,717,221 - Post , et al. April 6, 2
2004-04-06
Indium-boron dual halo MOSFET
App 20040061187 - Weber, Cory E. ;   et al.
2004-04-01
Method of fabricating dual threshold voltage n-channel and p-channel MOSFETS with a single extra masked implant operation
Grant 6,693,331 - Mistry , et al. February 17, 2
2004-02-17
Method of fabricating mosfet transistors with multiple threshold voltages by halo compensation and masks
App 20030203579 - Post, Ian R. ;   et al.
2003-10-30
Method of fabricating mosfet transistors with multiple threshold voltages by halo compensation and masks
App 20030190779 - Post, Ian R. ;   et al.
2003-10-09
Thin tensile layers in shallow trench isolation and method of making same
Grant 6,627,506 - Kuhn , et al. September 30, 2
2003-09-30
Method Of Fabricating Mosfet Transistors With Multiple Threshold Voltages By Halo Compensation And Masks
App 20030122198 - Post, Ian R. ;   et al.
2003-07-03
Method of fabricating MOSFET transistors with multiple threshold voltages by halo compensation and masks
Grant 6,586,294 - Post , et al. July 1, 2
2003-07-01
Method of fabricating dual threshold voltage n-channel and p-channel MOSFETs with a single extra masked implant operation
App 20030119248 - Mistry, Kaizad R. ;   et al.
2003-06-26
Method Of Fabricating Dual Threshold Voltage N-channel And P-channel Mosfets With A Single Extra Masked Implant Operation
App 20030094659 - MISTRY, KAIZAD R. ;   et al.
2003-05-22
Thin tensile layers in shallow trench isolation and method of making same
App 20020045325 - Kuhn, Kelin J. ;   et al.
2002-04-18
Thin tensile layers in shallow trench isolation and method of making same
Grant 6,368,931 - Kuhn , et al.
2002-04-09

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