loadpatents
name:-0.0068919658660889
name:-0.01007080078125
name:-0.00049090385437012
Popescu; Valeri Patent Filings

Popescu; Valeri

Patent Applications and Registrations

Patent applications and USPTO patent grants for Popescu; Valeri.The latest application filed is for "task-based performance resource management of computer systems".

Company Profile
0.11.5
  • Popescu; Valeri - Rancho Santa Fe CA
  • Popescu; Valeri - San Diego CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Task-Based Performance Resource Management of Computer Systems
App 20140331234 - Gibson; Gary Allen ;   et al.
2014-11-06
Control Of Processor Cache Memory Occupancy
App 20140201456 - Gibson; Gary Allen ;   et al.
2014-07-17
Fine grain performance resource management of computer systems
Grant 8,782,653 - Gibson , et al. July 15, 2
2014-07-15
Control of processor cache memory occupancy
Grant 8,677,071 - Gibson , et al. March 18, 2
2014-03-18
Control Of Processor Cache Memory Occupancy
App 20110238919 - Gibson; Gary Allen ;   et al.
2011-09-29
Fine Grain Performance Resource Management Of Computer Systems
App 20110239220 - Gibson; Gary Allen ;   et al.
2011-09-29
LogNet: a low cost, high reliability network for embedded systems
App 20020013805 - Popescu, Valeri
2002-01-31
Processor architecture providing for speculative execution of instructions with multiple predictive branching and handling of trap conditions
Grant 5,987,588 - Popescu , et al. November 16, 1
1999-11-16
Processor architecture providing speculative, out of order execution of instructions and trap handling
Grant 5,832,293 - Popescu , et al. November 3, 1
1998-11-03
Processor architecture providing speculative, out of order execution of instructions
Grant 5,708,841 - Popescu , et al. January 13, 1
1998-01-13
Processor architecture providing out-of-order execution
Grant 5,627,983 - Popescu , et al. May 6, 1
1997-05-06
Processor architecture having out-of-order execution, speculative branching, and giving priority to instructions which affect a condition code
Grant 5,625,837 - Popescu , et al. April 29, 1
1997-04-29
Processor architecture supporting multiple speculative branching
Grant 5,561,776 - Popescu , et al. October 1, 1
1996-10-01
Processor architecture having independently fetching issuing and updating operations of instructions which are sequentially assigned and stored in order fetched
Grant 5,487,156 - Popescu , et al. January 23, 1
1996-01-23

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