Polson; Anthony D.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Polson; Anthony D..The latest application filed is for "on-going reliability monitoring of integrated circuit chips in the field".

Company Profile

0.28.28

Polson; Anthony D. - Jericho VT
Polson; Anthony D. - Jericho Center VT
Polson; Anthony D - Jericho VT

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
On-going reliability monitoring of integrated circuit chips in the field Grant 9,310,426 - Anemikos , et al. April 12, 2	2016-04-12
Detecting chip alterations with light emission Grant 9,075,106 - Bernstein , et al. July 7, 2	2015-07-07
On-going Reliability Monitoring Of Integrated Circuit Chips In The Field App 20140088947 - Anemikos; Theodoros E. ; et al.	2014-03-27
Characterization of long range variability Grant 8,336,008 - Culp , et al. December 18, 2	2012-12-18
Method and system for evaluating timing in an integrated circuit Grant 7,962,874 - Foreman , et al. June 14, 2	2011-06-14
Characterization of Long Range Variability App 20110078641 - Culp; James A. ; et al.	2011-03-31
Method of laying out integrated circuit design based on known polysilicon perimeter densities of individual cells Grant 7,890,906 - Chadwick , et al. February 15, 2	2011-02-15
Detecting Chip Alterations with Light Emission App 20110026806 - Bernstein; Kerry ; et al.	2011-02-03
System and method to optimize semiconductor power by integration of physical design timing and product performance measurements Grant 7,877,714 - Anemikos , et al. January 25, 2	2011-01-25
Slack sensitivity to parameter variation based timing analysis Grant 7,870,525 - Foreman , et al. January 11, 2	2011-01-11
Method of generating wiring routes with matching delay in the presence of process variation Grant 7,865,861 - Habitz , et al. January 4, 2	2011-01-04
Integrated circuit with uniform polysilicon perimeter density, method and design structure Grant 7,849,433 - Chadwick , et al. December 7, 2	2010-12-07
Functional frequency testing of integrated circuits Grant 7,840,863 - Grise , et al. November 23, 2	2010-11-23
Functional frequency testing of integrated circuits Grant 7,840,864 - Grise , et al. November 23, 2	2010-11-23
Method of generating wiring routes with matching delay in the presence of process variation Grant 7,823,115 - Habitz , et al. October 26, 2	2010-10-26
Method of optimizing power usage of an integrated circuit design by tuning selective voltage binning cut point Grant 7,810,054 - Anemikos , et al. October 5, 2	2010-10-05
IC chip design modeling using perimeter density to electrical characteristic correlation Grant 7,805,693 - Chadwick , et al. September 28, 2	2010-09-28
High bandwidth low-latency semaphore mapped protocol (SMP) for multi-core systems on chips Grant 7,765,351 - Nsame , et al. July 27, 2	2010-07-27
Slack sensitivity to parameter variation based timing analysis Grant 7,716,616 - Foreman , et al. May 11, 2	2010-05-11
Functional Frequency Testing Of Integrated Circuits App 20100088561 - Grise; Gary D. ; et al.	2010-04-08
Functional Frequency Testing Of Integrated Circuits App 20100088562 - Grise; Gary D. ; et al.	2010-04-08
System and method of analyzing timing effects of spatial distribution in circuits Grant 7,680,626 - Hathaway , et al. March 16, 2	2010-03-16
Method Of Laying Out Integrated Circuit Design Based On Known Polysilicon Perimeter Densities Of Individual Cells App 20090282380 - Chadwick; Laura S. ; et al.	2009-11-12
Integrated Circuit With Uniform Polysilicon Perimeter Density, Method And Design Structure App 20090278222 - Chadwick; Laura S. ; et al.	2009-11-12
Method To Optimize Power By Tuning The Selective Voltage Binning Cut Point App 20090228843 - Anemikos; Theodoros E. ; et al.	2009-09-10
System And Method To Optimize Semiconductor Power By Integration Of Physical Design Timing And Product Performance Measurements App 20090217221 - ANEMIKOS; Theodoros E. ; et al.	2009-08-27
Ic Chip Design Modeling Using Perimeter Density To Electrical Characteristic Correlation App 20090210834 - Chadwick; Laura S. ; et al.	2009-08-20
Design Structure for an Integrated Circuit Having State-Saving Input-Output Circuitry and a Method of Testing Such an Integrated Circuit App 20090115447 - Anemikos; Theodoros E. ; et al.	2009-05-07
Clock-skew tuning apparatus and method Grant 7,521,973 - Anemikos , et al. April 21, 2	2009-04-21
Method and structure for chip-level testing of wire delay independent of silicon delay Grant 7,489,204 - Habitz , et al. February 10, 2	2009-02-10
Design structure for monitoring cross chip delay variation on a semiconductor device Grant 7,487,487 - Polson , et al. February 3, 2	2009-02-03
Method And System For Evaluating Timing In An Integrated Circuit App 20080313590 - FOREMAN; Eric A. ; et al.	2008-12-18
Method and system for evaluating timing in an integrated circuit Grant 7,444,608 - Foreman , et al. October 28, 2	2008-10-28
High Bandwidth Low-Latency Semaphore Mapped Protocol (SMP) For Multi-Core Systems On Chips App 20080229006 - Nsame; Pascal A. ; et al.	2008-09-18
Slack Sensitivity To Parameter Variation Based Timing Analysis App 20080216036 - Foreman; Eric A. ; et al.	2008-09-04
Method of generating wiring routes with matching delay in the presence of process variation Grant 7,418,689 - Habitz , et al. August 26, 2	2008-08-26
Method of Generating Wiring Routes with Matching Delay in the Presence of Process Variation App 20080201683 - Habitz; Peter A. ; et al.	2008-08-21
Method of Generating Wiring Routes with Matching Delay in the Presence of Process Variation App 20080195993 - Habitz; Peter A. ; et al.	2008-08-14
Slack sensitivity to parameter variation based timing analysis Grant 7,401,307 - Foreman , et al. July 15, 2	2008-07-15
Integrated Circuit Having State-Saving Input-Output Circuitry and a Method of Testing Such an Integrated Circuit App 20080129330 - Anemikos; Theodoros ; et al.	2008-06-05
Slack Sensitivity To Parameter Variation Based Timing Analysis App 20080052656 - Foreman; Eric A. ; et al.	2008-02-28
Functional Frequency Testing Of Integrated Circuits App 20070283201 - Grise; Gary D. ; et al.	2007-12-06
Method and system for performing shapes correction of a multi-cell reticle photomask design Grant 7,302,673 - Habitz , et al. November 27, 2	2007-11-27
Functional frequency testing of integrated circuits Grant 7,290,191 - Grise , et al. October 30, 2	2007-10-30
System and method of analyzing timing effects of spatial distribution in circuits Grant 7,280,939 - Hathaway , et al. October 9, 2	2007-10-09
System And Method Of Analyzing Timing Effects Of Spatial Distribution In Circuits App 20070220345 - HATHAWAY; David J. ; et al.	2007-09-20
Method For Reticle Shapes Analysis And Correction App 20070061771 - Habitz; Peter Anton ; et al.	2007-03-15
Method And Structure For Chip-level Testing Of Wire Delay Independent Of Silicon Delay App 20070001682 - Habitz; Peter A. ; et al.	2007-01-04
Method Of Generating Wiring Routes With Matching Delay In The Presence Of Process Variation App 20060248488 - Habitz; Peter A. ; et al.	2006-11-02
Method And System For Evaluating Timing In An Integated Circuit App 20060195807 - Foreman; Eric A. ; et al.	2006-08-31
Method and system for evaluating timing in an integrated circuit Grant 7,089,143 - Foreman , et al. August 8, 2	2006-08-08
Slack Sensitivity To Parameter Variation Based Timing Analysis App 20060101361 - Foreman; Eric A. ; et al.	2006-05-11
Functional Frequency Testing Of Integrated Circuits App 20060041802 - Grise; Gary D. ; et al.	2006-02-23
System And Method Of Analyzing Timing Effects Of Spatial Distribution In Circuits App 20050246117 - Hathaway, David J. ; et al.	2005-11-03
Method And System For Evaluating Timing In An Integrated Circuit App 20050246116 - Foreman, Eric A. ; et al.	2005-11-03

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