loadpatents
name:-0.0057699680328369
name:-0.0091969966888428
name:-0.0014321804046631
Pollock; Steven J. Patent Filings

Pollock; Steven J.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Pollock; Steven J..The latest application filed is for "reducing current variation when switching clocks".

Company Profile
0.9.6
  • Pollock; Steven J. - Allentown PA
  • Pollock; Steven J. - US
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Modifying data streams without reordering in a multi-thread, multi-flow network processor
Grant 9,461,930 - Pollock , et al. October 4, 2
2016-10-04
Dynamic configuration of processing modules in a network communications processor architecture
Grant 9,444,757 - Pekcan , et al. September 13, 2
2016-09-13
Reducing Current Variation When Switching Clocks
App 20150091620 - Pollock; Steven J.
2015-04-02
Changing a flow identifier of a packet in a multi-thread, multi-flow network processor
Grant 8,949,582 - Mital , et al. February 3, 2
2015-02-03
Transaction performance monitoring in a processor bus bridge
Grant 8,489,792 - Byrne , et al. July 16, 2
2013-07-16
Modifying Data Streams without Reordering in a Multi-Thread, Multi-Flow Network Communications Processor Architecture
App 20130089099 - Pollock; Steven J. ;   et al.
2013-04-11
Changing a Flow Identifier of a Packet in a Multi-Thread, Multi-Flow Network Processor
App 20130089098 - Mital; Deepak ;   et al.
2013-04-11
Dynamic Configuration Of Processing Modules In A Network Communications Processor Architecture
App 20110289179 - Pekcan; Hakan I. ;   et al.
2011-11-24
Transaction Performance Monitoring In A Processor Bus Bridge
App 20110225337 - Byrne; Richard J. ;   et al.
2011-09-15
Inter-DSP signaling in a multiple DSP environment
Grant 7,389,368 - Burroughs , et al. June 17, 2
2008-06-17
Programmable delay circuit having reduced insertion delay
Grant 7,382,170 - Pollock June 3, 2
2008-06-03
Programmable delay circuit having reduced insertion delay
App 20070241800 - Pollock; Steven J.
2007-10-18
Inter-DSP data exchange in a multiple DSP environment
Grant 6,691,190 - Burroughs , et al. February 10, 2
2004-02-10

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