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Learning framework for software-hardware model generation and verification
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Deep Neural Network On Field-programmable Gate Array
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Interactive-aware Clustering Of Stable States
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Native Code Generation for Cloud Services
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Random Sequence Generation For Gene Simulations
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Bit-serial Linear Algebra Processor
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Precision data access using differential data
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Precision data access using differential data
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Hardware Compilation Of Cascaded Grammars
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Learning Framework For Software-hardware Model Generation And Verification
App 20190087513 - Mukherjee; Rajdeep ; et al. | 2019-03-21 |
Hardware compilation of cascaded grammars
Grant 10,198,646 - Atasu , et al. Fe | 2019-02-05 |
Linear FE system solver with dynamic multi-grip precision
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Non-deterministic finite state machine module for use in a regular expression matching system
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Index Based Memory Access
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Accelerated Content Analytics Based On A Hierarchical Data-flow-graph Representation
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Hardware Compilation Of Cascaded Grammars
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Accelerated content analytics based on a hierarchical data-flow-graph representation
Grant 9,858,056 - Atasu , et al. January 2, 2 | 2018-01-02 |
Interposer for dynamic mapping of API calls
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Differential Data Access
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Adaptable and extensible runtime and system for heterogeneous computer systems
Grant 9,557,976 - Angerer , et al. January 31, 2 | 2017-01-31 |
Adaptable and extensible runtime and system for heterogeneous computer systems
Grant 9,557,975 - Angerer , et al. January 31, 2 | 2017-01-31 |
Linear Fe System Solver With Dynamic Multi-grid Precision
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SRAM array comprising multiple cell cores
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Differential Data Access
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Sram Array Comprising Multiple Cell Cores
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Adaptable and Extensible Runtime and System for Heterogeneous Computer Systems
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Adaptable and Extensible Runtime and System for Heterogeneous Computer Systems
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Defective memory column replacement with load isolation
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Integrated circuit schematics having imbedded scaling information for generating a design instance
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Non-deterministic Finite State Machine Module For Use In A Regular Expression Matching System
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Defective Memory Column Replacement With Load Isolation
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Integrated Circuit Schematics Having Imbedded Scaling Information For Generating A Design Instance
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Method and system for generating a placement layout of a VLSI circuit design
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Method and System for Generating a Placement Layout of a VLSI Circuit Design
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Global Bit Line Restore By Most Significant Bit Of An Address Line
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Interleave Memory Array Arrangement
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