| Patent | Date |
|---|
Instruction having bit field designating status bits protected from modification corresponding to arithmetic logic unit result
Grant 6,173,394 - Guttag , et al. January 9, 2 | 2001-01-09 |
Three input arithmetic logic unit with barrel rotator
Grant 6,116,768 - Guttag , et al. September 12, 2 | 2000-09-12 |
Three input arithmetic logic unit with shifter
Grant 6,098,163 - Guttag , et al. August 1, 2 | 2000-08-01 |
Three input arithmetic logic unit with shifter and/or mask generator
Grant 5,995,748 - Guttag , et al. November 30, 1 | 1999-11-30 |
Three input arithmetic logic unit with shifter and mask generator
Grant 5,974,539 - Guttag , et al. October 26, 1 | 1999-10-26 |
Base address generation in a multi-processing system having plural memories with a unified address space corresponding to each processor
Grant 5,761,726 - Guttag , et al. June 2, 1 | 1998-06-02 |
Hardware branching employing loop control registers loaded according to status of sections of an arithmetic logic unit divided into a plurality of sections
Grant 5,734,880 - Guttag , et al. March 31, 1 | 1998-03-31 |
Memory store from a selected one of a register pair conditional upon the state of a selected status bit
Grant 5,696,959 - Guttag , et al. December 9, 1 | 1997-12-09 |
Three input arithmetic logic unit with shifting means at one input forming a sum/difference of two inputs logically anded with a third input logically ored with the sum/difference logically anded with an inverse of the third input
Grant 5,696,954 - Guttag , et al. December 9, 1 | 1997-12-09 |
Data processor having capability to perform both floating point operations and memory access in response to a single instruction
Grant 5,673,407 - Poland , et al. September 30, 1 | 1997-09-30 |
Iterative division apparatus, system and method employing left most one's detection and left most one's detection with exclusive or
Grant 5,644,524 - Van Aken , et al. July 1, 1 | 1997-07-01 |
Arithmetic logic unit having plural independent sections and register storing resultant indicator bit from every section
Grant 5,640,578 - Balmer , et al. June 17, 1 | 1997-06-17 |
Three input arithmetic logic unit with controllable shifter and mask generator
Grant 5,634,065 - Guttag , et al. May 27, 1 | 1997-05-27 |
Three input arithmetic logic unit with mask generator
Grant 5,600,847 - Guttag , et al. February 4, 1 | 1997-02-04 |
Three input arithmetic logic unit with mask generator
Grant 5,590,350 - Guttag , et al. December 31, 1 | 1996-12-31 |
Pixel block transfer with transparency
Grant 5,493,646 - Guttag , et al. February 20, 1 | 1996-02-20 |
Plural memory access address generation employing guide table entries forming linked list
Grant 5,487,146 - Guttag , et al. January 23, 1 | 1996-01-23 |
Iterative division apparatus, system and method forming plural quotient bits per iteration
Grant 5,442,581 - Poland August 15, 1 | 1995-08-15 |
Electronic calculator system having high order math capability
Grant 4,298,949 - Poland November 3, 1 | 1981-11-03 |
Microprocessor system having high order capability
Grant RE30,671 - Poland July 7, 1 | 1981-07-07 |
Microprocessor system having high order capability
Grant 4,153,937 - Poland May 8, 1 | 1979-05-08 |
Calculator program security system
Grant 4,139,893 - Poland February 13, 1 | 1979-02-13 |
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