| Patent | Date |
|---|
Computer implemented method for determining intrinsic parameter in a stacked nanowires MOSFET
Grant 10,914,703 - Rozeau , et al. February 9, 2 | 2021-02-09 |
Computer Implemented Method For Determining Intrinsic Parameter In A Stacked Nanowires Mosfet
App 20180156749 - ROZEAU; Olivier ; et al. | 2018-06-07 |
Fdsoi-type Field-effect Transistors
App 20180097014 - Barral; Vincent ; et al. | 2018-04-05 |
Computer Implemented Method For Calculating A Charge Density At A Gate Interface Of A Double Gate Transistor
App 20160019327 - POIROUX; Thierry ; et al. | 2016-01-21 |
Computer implemented method for calculating a charge density at a gate interface of a double gate transistor
Grant 9,235,668 - Poiroux , et al. January 12, 2 | 2016-01-12 |
Manufacturing method for a device with transistors strained by silicidation of source and drain zones
Grant 9,093,552 - Nemouchi , et al. July 28, 2 | 2015-07-28 |
Process for producing an integrated circuit
Grant 8,877,622 - Poiroux , et al. November 4, 2 | 2014-11-04 |
Field effect transistor with alternate electrical contacts
Grant 8,866,225 - Mayer , et al. October 21, 2 | 2014-10-21 |
Method of producing a device with transistors strained by means of an external layer
Grant 8,664,104 - Nemouchi , et al. March 4, 2 | 2014-03-04 |
Method of fabricating an electromechanical component using graphene
Grant 8,656,584 - Gabriel , et al. February 25, 2 | 2014-02-25 |
Process for producing two interleaved patterns on a substrate
Grant 8,598,038 - Morand , et al. December 3, 2 | 2013-12-03 |
Process For Producing An Integrated Circuit
App 20130252412 - Poiroux; Thierry ; et al. | 2013-09-26 |
Method for manufacturing a strained channel MOS transistor
Grant 8,530,292 - Morand , et al. September 10, 2 | 2013-09-10 |
Method Of Producing A Device With Transistors Strained By Means Of An External Layer
App 20130214362 - NEMOUCHI; Fabrice ; et al. | 2013-08-22 |
Manufacturing Method For A Device With Transistors Strained By Silicidation Of Source And Drain Zones
App 20130214363 - NEMOUCHI; Fabrice ; et al. | 2013-08-22 |
Method for making asymmetric double-gate transistors
Grant 8,399,316 - Vinet , et al. March 19, 2 | 2013-03-19 |
Method for stabilizing germanium nanowires obtained by condensation
Grant 8,349,667 - Saracco , et al. January 8, 2 | 2013-01-08 |
Method for fabricating asymmetric double-gate transistors by which asymmetric and symmetric double-gate transistors can be made on the same substrate
Grant 8,324,057 - Vinet , et al. December 4, 2 | 2012-12-04 |
Method for making asymmetric double-gate transistors by which asymmetric and symmetric double-gate transistors can be made on the same substrate
Grant 8,232,168 - Vinet , et al. July 31, 2 | 2012-07-31 |
Method For Manufacturing A Strained Channel Mos Transistor
App 20120153394 - Morand; Yves ; et al. | 2012-06-21 |
Method for fabricating asymmetric double-gate transistors by which asymmetric and symmetric double-gate transistors can be made on the same substrate
Grant 8,105,906 - Vinet , et al. January 31, 2 | 2012-01-31 |
Process For Producing Two Interleaved Patterns On A Substrate
App 20120021606 - Morand; Yves ; et al. | 2012-01-26 |
Method for producing a transistor with metallic source and drain
Grant 8,021,986 - Previtali , et al. September 20, 2 | 2011-09-20 |
Method for making a transistor with metallic source and drain
Grant 8,021,934 - Vinet , et al. September 20, 2 | 2011-09-20 |
Microelectronic device provided with transistors coated with a piezoelectric layer
Grant 7,968,945 - Lolivier , et al. June 28, 2 | 2011-06-28 |
Conception Of An Electro-mechanical Component For A Micro- Or Nano-system Equipped With A Bar Forming An Axis Of Rotation Of The Component And Coated In Graphene
App 20110067985 - GABRIEL; Jean-Christophe ; et al. | 2011-03-24 |
Method For Stabilizing Germanium Nanowires Obtained By Condensation
App 20110059598 - SARACCO; Emeline ; et al. | 2011-03-10 |
Method For Producing A Transistor With Metallic Source And Drain
App 20110003443 - Previtali; Bernard ; et al. | 2011-01-06 |
Method For Fabricating Asymmetric Double-gate Transistors By Which Asymmetric And Symmetric Double-gate Transistors Can Be Made On The Same Substrate
App 20100320541 - Vinet; Maud ; et al. | 2010-12-23 |
Method For Making Asymmetric Double-gate Transistors By Which Asymmetric And Symmetric Double-gate Transistors Can Be Made On The Same Substrate
App 20100317167 - Vinet; Maud ; et al. | 2010-12-16 |
Transistor with a germanium-based channel encased by a gate electrode and method for producing one such transistor
Grant 7,829,916 - Morand , et al. November 9, 2 | 2010-11-09 |
Method For Making Asymmetric Double-gate Transistors
App 20100178743 - Vinet; Maud ; et al. | 2010-07-15 |
Field Effect Transistor With Alternate Electrical Contacts
App 20100155843 - Mayer; Frederic ; et al. | 2010-06-24 |
Method For Fabricating Asymmetric Double-gate Transistors By Which Asymmetric And Symmetric Double-gate Transistors Can Be Made On The Same Substrate
App 20100096700 - Vinet; Maud ; et al. | 2010-04-22 |
Method For Making A Transistor With Metallic Source And Drain
App 20090286363 - VINET; Maud ; et al. | 2009-11-19 |
Transistor with a germanium-based channel encased by a gate electrode and method for producing one such transistor
App 20090127584 - Morand; Yves ; et al. | 2009-05-21 |
Method for insulating patterns formed in a thin film of oxidizable semi-conducting material
Grant 7,473,588 - Vinet , et al. January 6, 2 | 2009-01-06 |
Microelectronic Device Provided with Transistors Coated with a Piezoelectric Layer
App 20080290384 - Lolivier; Jerome ; et al. | 2008-11-27 |
Method for producing a component comprising at least one germanium-based element and component obtained by such a method
Grant 7,361,592 - Morand , et al. April 22, 2 | 2008-04-22 |
Method for producing a component comprising at least one germanium-based element and component obtained by such a method
App 20060276052 - Morand; Yves ; et al. | 2006-12-07 |
Method for insulating patterns formed in a thin film of oxidizable semi-conducting material
App 20060121653 - Vinet; Maud ; et al. | 2006-06-08 |
Process and device for evaluating a CMOS logical cell
Grant 6,779,161 - Poiroux , et al. August 17, 2 | 2004-08-17 |
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