Pogge; H. Bernhard

Patent Applications and Registrations

Patent applications and USPTO patent grants for Pogge; H. Bernhard.The latest application filed is for "chip and wafer integration process using vertical connections".

Company Profile

0.35.19

Pogge; H. Bernhard - Hopewell Junction NY US
Pogge; H. Bernhard - Wappingers Falls NY
Pogge; H. Bernhard - Dutchess County NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Structure and method to improve current-carrying capabilities of C4 joints Grant 8,367,543 - Farooq , et al. February 5, 2	2013-02-05
Metal filled through via structure for providing vertical wafer-to-wafer interconnection Grant 7,821,120 - Pogge , et al. October 26, 2	2010-10-26
Chip and wafer integration process using vertical connections Grant 7,564,118 - Pogge , et al. July 21, 2	2009-07-21
Chip And Wafer Integration Process Using Vertical Connections App 20080230891 - Pogge; H. Bernhard ; et al.	2008-09-25
Chip and wafer integration process using vertical connections Grant 7,388,277 - Pogge , et al. June 17, 2	2008-06-17
Metal Filled Through Via Structure For Providing Vertical Wafer-to-wafer Interconnection App 20080105976 - Pogge; H. Bernhard ; et al.	2008-05-08
Three-dimensional device fabrication method Grant 7,354,798 - Pogge , et al. April 8, 2	2008-04-08
Metal filled through via structure for providing vertical wafer-to-wafer interconnection Grant 7,344,959 - Pogge , et al. March 18, 2	2008-03-18
Integrated Electronic Chip And Interconnect Device And Process For Making The Same App 20070252287 - Pogge; H. Bernhard ; et al.	2007-11-01
Structure And Method To Improve Current-carrying Capabilities Of C4 Joints App 20070222073 - Farooq; Mukta Ghate ; et al.	2007-09-27
Integrated electronic chip and interconnect device and process for making the same App 20060278998 - Pogge; H. Bernhard ; et al.	2006-12-14
Three-dimensional integrated CMOS-MEMS device and process for making the same Grant 7,071,031 - Pogge , et al. July 4, 2	2006-07-04
Three-dimensional device fabrication method App 20060121690 - Pogge; H Bernhard ; et al.	2006-06-08
Process for making fine pitch connections between devices and structure made by the process Grant 7,049,697 - Pogge , et al. May 23, 2	2006-05-23
Method and device for heat dissipation in semiconductor modules Grant 7,049,695 - Pogge May 23, 2	2006-05-23
Process for making fine pitch connections between devices and structure made by the process App 20050173800 - Pogge, H. Bernhard ; et al.	2005-08-11
Chip and wafer integration process using vertical connections App 20050121711 - Pogge, H. Bernhard ; et al.	2005-06-09
Method Of Fabricating Integrated Electronic Chip With An Interconnect Device App 20050056942 - Pogge, H. Bernhard ; et al.	2005-03-17
Integrated Electronic Chip And Interconnect Device And Process For Making The Same App 20050056943 - Pogge, H. Bernhard ; et al.	2005-03-17
Method of fabricating integrated electronic chip with an interconnect device Grant 6,864,165 - Pogge , et al. March 8, 2	2005-03-08
Chip and wafer integration process using vertical connections Grant 6,856,025 - Pogge , et al. February 15, 2	2005-02-15
Three-dimensional integrated CMOS-MEMS device and process for making the same Grant 6,835,589 - Pogge , et al. December 28, 2	2004-12-28
Three-dimensional integrated CMOS-MEMS device and process for making the same App 20040097004 - Pogge, H. Bernhard ; et al.	2004-05-20
Three-dimensional integrated CMOS-MEMS device and process for making the same App 20040097002 - Pogge, H. Bernhard ; et al.	2004-05-20
Process for making fine pitch connections between devices and structure made by the process Grant 6,737,297 - Pogge , et al. May 18, 2	2004-05-18
Method for chip testing Grant 6,730,529 - Kalter , et al. May 4, 2	2004-05-04
Chip and wafer integration process using vertical connections App 20030215984 - Pogge, H. Bernhard ; et al.	2003-11-20
Fabrication of a hybrid integrated circuit device including an optoelectronic chip Grant 6,640,021 - Pogge , et al. October 28, 2	2003-10-28
Chip and wafer integration process using vertical connections Grant 6,599,778 - Pogge , et al. July 29, 2	2003-07-29
Chip And Wafer Integration Process Using Vertical Connections App 20030111733 - Pogge, H. Bernhard ; et al.	2003-06-19
Fabrication of a hybrid integrated circuit device including an optoelectronic chip App 20030108269 - Pogge, H. Bernhard ; et al.	2003-06-12
Process for making fine pitch connections between devices and structure made by the process App 20030015788 - Pogge, H. Bernhard ; et al.	2003-01-23
Process for making fine pitch connections between devices and structure made by the process Grant 6,444,560 - Pogge , et al. September 3, 2	2002-09-03
Structure And Process For Multi-chip Chip Attach With Reduced Risk Of Electrostatic Discharge Damage App 20020106893 - Furukawa, Toshiharu ; et al.	2002-08-08
Structure and process for multi-chip chip attach with reduced risk of electrostatic discharge damage Grant 6,429,045 - Furukawa , et al. August 6, 2	2002-08-06
Three-dimensional chip stacking assembly Grant 6,355,501 - Fung , et al. March 12, 2	2002-03-12
Wafer thickness compensation for interchip planarity App 20020011652 - Pogge, H. Bernhard	2002-01-31
Wafer thickness compensation for interchip planarity Grant 6,333,553 - Pogge December 25, 2	2001-12-25
Double-sided Wafer Exposure Method And Device App 20010001900 - POGGE, H. BERNHARD ; et al.	2001-05-31
Process for precision alignment of chips for mounting on a substrate Grant 6,110,806 - Pogge August 29, 2	2000-08-29
Process for precise multichip integration and product thereof Grant 6,066,513 - Pogge , et al. May 23, 2	2000-05-23
Structure for precision multichip assembly Grant 6,025,638 - Pogge , et al. February 15, 2	2000-02-15
Very dense chip package Grant 5,998,868 - Pogge , et al. December 7, 1	1999-12-07
Method for chip testing Grant 5,899,703 - Kalter , et al. May 4, 1	1999-05-04
Very dense integrated circuit package and method for forming the same Grant 5,866,443 - Pogge , et al. February 2, 1	1999-02-02
Very dense integrated circuit package Grant 5,814,885 - Pogge , et al. September 29, 1	1998-09-29
Very dense integrated circuit package Grant 5,770,884 - Pogge , et al. June 23, 1	1998-06-23
Soi fabrication process Grant 5,681,775 - Pogge October 28, 1	1997-10-28
Thin film resistor and method for producing same Grant 5,081,439 - Natzle , et al. January 14, 1	1992-01-14
Silicon integrated circuit region containing implanted arsenic and germanium Grant 4,137,103 - Mader , et al. January 30, 1	1979-01-30
Minimization of misfit dislocations in silicon by double implantation of arsenic and germanium Grant 4,111,719 - Mader , et al. September 5, 1	1978-09-05
High power semiconductor device Grant 3,961,353 - Aboaf , et al. June 1, 1	1976-06-01
Method of fabricating semiconductor device embodying dielectric isolation Grant 3,919,060 - Pogge , et al. November 11, 1	1975-11-11