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Po; Chen-Hao Patent Filings

Po; Chen-Hao

Patent Applications and Registrations

Patent applications and USPTO patent grants for Po; Chen-Hao.The latest application filed is for "differential type non-volatile memory circuit".

Company Profile
3.20.18
  • Po; Chen-Hao - Hsinchu County TW
  • Po; Chen-Hao - Hsinchu TW
  • Po; Chen-Hao - Hsinchu City TW
  • Po; Chen-Hao - Taipei County N/A TW
  • Po; Chen-Hao - Sijhih TW
  • Po; Chen-Hao - Sijhih City TW
  • Po; Chen-Hao - Hsin-Chu TW
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Differential type sensing circuit with differential input and output terminal pair
Grant 10,930,746 - Po , et al. February 23, 2
2021-02-23
Differential Type Non-volatile Memory Circuit
App 20190325924 - Po; Chen-Hao ;   et al.
2019-10-24
Non-volatile memory with a new sensing sequence control method
Grant 10,410,691 - Po Sept
2019-09-10
Non-volatile Memory With A New Sensing Sequence Control Method
App 20190214059 - Po; Chen-Hao
2019-07-11
Memory array with one shared deep doped region
Grant 10,255,980 - Lai , et al.
2019-04-09
Memory Array With One Shared Deep Doped Region
App 20180190357 - Lai; Tsung-Mu ;   et al.
2018-07-05
Memory array with one shared deep doped region
Grant 9,941,011 - Lai , et al. April 10, 2
2018-04-10
Driving circuit for non-volatile memory
Grant 9,882,566 - Po , et al. January 30, 2
2018-01-30
Memory array capable of performing byte erase operation
Grant 9,847,133 - Lai , et al. December 19, 2
2017-12-19
Driving circuit for non-volatile memory
Grant 9,786,340 - Po October 10, 2
2017-10-10
Memory Array With One Shared Deep Doped Region
App 20170206968 - Lai; Tsung-Mu ;   et al.
2017-07-20
Memory Array Capable Of Performing Byte Erase Operation
App 20170206970 - Lai; Tsung-Mu ;   et al.
2017-07-20
Driving Circuit For Non-volatile Memory
App 20170206941 - Po; Chen-Hao
2017-07-20
Driving circuit for non-volatile memory
Grant 9,633,734 - Po April 25, 2
2017-04-25
Voltage switch circuit
Grant 9,520,196 - Po December 13, 2
2016-12-13
Voltage Switch Circuit
App 20160005487 - Po; Chen-Hao
2016-01-07
Voltage switch circuit
Grant 9,224,490 - Po December 29, 2
2015-12-29
Memory having a voltage switch circuit with one bias voltage changed in each state of conditioning
Grant 9,190,415 - Po November 17, 2
2015-11-17
Non-volatile memory apparatus and data verification method thereof
Grant 9,019,780 - Lin , et al. April 28, 2
2015-04-28
Non-volatile Memory Apparatus And Data Verification Method Thereof
App 20150098278 - Lin; Yih-Lang ;   et al.
2015-04-09
Memory having a voltage switch circuit with one bias voltage changed in each state of conditioning
App 20150092507 - Po; Chen-Hao
2015-04-02
Voltage switch circuit
Grant 8,841,942 - Po , et al. September 23, 2
2014-09-23
Single-ended Sense Amplifier Circuit
App 20140177350 - Chen; Yung-Jui ;   et al.
2014-06-26
Voltage Switch Circuit
App 20140103988 - Po; Chen-Hao ;   et al.
2014-04-17
Voltage switch circuit produced by logic circuit manufacturing process capable of withstanding high voltage stress
Grant 8,653,878 - Po , et al. February 18, 2
2014-02-18
Voltage Switch Circuit
App 20130099850 - Po; Chen-Hao ;   et al.
2013-04-25
Voltage level shifting apparatus
Grant 8,373,485 - Po , et al. February 12, 2
2013-02-12
Volatge Level Shifting Apparatus
App 20120268188 - Po; Chen-Hao ;   et al.
2012-10-25
Verify While Write Scheme For Non-volatile Memory Cell
App 20110194355 - Po; Chen-Hao
2011-08-11
2T SRAM cell structure
Grant 7,889,541 - Shih , et al. February 15, 2
2011-02-15
2t Sram Cell Structure
App 20090257273 - SHIH; WEI-CHIANG ;   et al.
2009-10-15
Serial peripheral interface memory device with an accelerated parallel mode
Grant 7,397,717 - Chen , et al. July 8, 2
2008-07-08
Serial peripheral interface memory device with an accelerated parallel mode
App 20060268642 - Chen; Han-Sung ;   et al.
2006-11-30
Circuit and method for tuning a reference bit line loading to a sense amplifier by optionally cutting a capacitive reference bit line
Grant 6,795,350 - Chen , et al. September 21, 2
2004-09-21
Circuit and method for tuning a reference bit line loading to a sense amplifier by optionally cutting a capacitive reference bit line
App 20040008546 - Chen, Han-Sung ;   et al.
2004-01-15

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