PINEDA DE GYVEZ; JOSE
Patent Applications and Registrations
Patent applications and USPTO patent grants for PINEDA DE GYVEZ; JOSE.The latest application filed is for "method, and a synchronous digital circuit, for preventing propagation of set-up timing data errors".
- PINEDA DE GYVEZ; JOSE - Eindhoven NL
| Patent | Date |
|---|---|
| Method, And A Synchronous Digital Circuit, For Preventing Propagation Of Set-up Timing Data Errors App 20180224886 - FABRIE; SEBASTIEN ; et al. | 2018-08-09 |
| Level shifter and approach therefor Grant 9,917,588 - Blutman , et al. March 13, 2 | 2018-03-13 |
| Configurable power domain and method Grant 9,912,335 - Kapoor , et al. March 6, 2 | 2018-03-06 |
| Level Shifter And Approach Therefor App 20170012628 - Blutman; Kristof ; et al. | 2017-01-12 |
| Configurable Power Domain And Method App 20170012627 - Kapoor; Ajay ; et al. | 2017-01-12 |
| Parallel execution of instructions in processing units and adjusting power mode based on monitored data dependency over a period of time Grant 9,465,614 - Fatemi , et al. October 11, 2 | 2016-10-11 |
| Clock buffer Grant 9,065,439 - Sharma , et al. June 23, 2 | 2015-06-23 |
| Energy efficient microprocessor platform based on instructional level parallelism Grant 9,009,506 - Fatemi , et al. April 14, 2 | 2015-04-14 |
| Integrated Circuit, Electronic Device And Instruction Scheduling Method App 20140258686 - Fatemi; Hamed ; et al. | 2014-09-11 |
| Clock Buffer App 20140225645 - SHARMA; Vibhu ; et al. | 2014-08-14 |
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