Pillay; Sanjay

Patent Applications and Registrations

Patent applications and USPTO patent grants for Pillay; Sanjay.The latest application filed is for "functional safety synthesis".

Company Profile

6.13.12

Pillay; Sanjay - Round Rock TX
Pillay; Sanjay - Aust TX
Pillay; Sanjay - Austin TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Mobile application development device Grant 11,403,072 - Pillay , et al. August 2, 2	2022-08-02
Parallel fault simulator with back propagation enhancement Grant 11,036,604 - Pillay , et al. June 15, 2	2021-06-15
Functional safety synthesis Grant 10,796,047 - Pillay , et al. October 6, 2	2020-10-06
Fault campaign in mixed signal environment Grant 10,775,430 - Pillay , et al. Sept	2020-09-15
Systems and methods for analyzing failure rates due to soft/hard errors in the design of a digital electronic device Grant 10,768,227 - Pillay , et al. Sep	2020-09-08
Low power VLSI designs using circuit failure in sequential cells as low voltage check for limit of operation Grant 10,522,237 - Pillay Dec	2019-12-31
Functional Safety Synthesis App 20190228125 - Pillay; Sanjay ; et al.	2019-07-25
Fault Campaign In Mixed Signal Environment App 20190187207 - Pillay; Sanjay ; et al.	2019-06-20
Parallel Fault Simulator With Back Propagation Enhancement App 20190171539 - Pillay; Sanjay ; et al.	2019-06-06
Systems And Methods For Analyzing Failure Rates Due To Soft/hard Errors In The Design Of A Digital Electronic Device App 20180364306 - Pillay; Sanjay ; et al.	2018-12-20
Systems and methods for analyzing soft errors in a design and reducing the associated failure rates thereof Grant 9,991,008 - Pillay June 5, 2	2018-06-05
Build deployment automation for information technology mangement Grant 9,898,269 - Pillay , et al. February 20, 2	2018-02-20
Systems And Methods For Analyzing Soft Errors In A Design And Reducing The Associated Failure Rates Thereof App 20170213602 - Pillay; Sanjay	2017-07-27
Low Power Vlsi Designs Using Circuit Failure In Sequential Cells As Low Voltage Check For Limit Of Operation App 20170212972 - Pillay; Sanjay	2017-07-27
Caller validation Grant 9,521,141 - Pillay December 13, 2	2016-12-13
Build Deployment Automation for Information Technology Mangement App 20160139916 - Pillay; Sanjay ; et al.	2016-05-19
Build deployment automation for information technology management Grant 9,323,513 - Pillay , et al. April 26, 2	2016-04-26
Build Deployment Automation for Information Technology Management App 20150248280 - Pillay; Sanjay ; et al.	2015-09-03
Caller Validation App 20150229631 - Pillay; Sanjay	2015-08-13
Scan cells with minimized shoot-through and scan chains and integrated circuits using the same Grant 7,747,917 - Putman , et al. June 29, 2	2010-06-29
Processor and processing method for reusing arbitrary sections of program code Grant 7,596,681 - Wiese , et al. September 29, 2	2009-09-29
Scan cells with minimized shoot-through and scan chains and integrated circuits using the same App 20080307280 - Putman; Richard ; et al.	2008-12-11
Processor and processing method for reusing arbitrary sections of program code App 20070239973 - Wiese; Ronald D. ; et al.	2007-10-11
Variable duty cycle clock generation circuits and methods and systems using the same Grant 6,847,244 - Pillay , et al. January 25, 2	2005-01-25
Variable duty cycle clock generation circuits and methods and systems using the same App 20040135608 - Pillay, Sanjay ; et al.	2004-07-15

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