Pileggi; Larry

Patent Applications and Registrations

Patent applications and USPTO patent grants for Pileggi; Larry.The latest application filed is for "high performance merge sort with scalable parallelization and full-throughput reduction".

Company Profile

1.5.5

Pileggi; Larry - Pittsburgh PA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
High performance merge sort with scalable parallelization and full-throughput reduction Grant 11,249,720 - Sadi , et al. February 15, 2	2022-02-15
High Performance Merge Sort With Scalable Parallelization And Full-throughput Reduction App 20200159492 - Sadi; Fazle ; et al.	2020-05-21
Method and apparatus for thermal modeling and analysis of semiconductor chip designs Grant 8,082,137 - Li , et al. December 20, 2	2011-12-20
Statistical optimization and design method for analog and digital circuits Grant 7,669,150 - Li , et al. February 23, 2	2010-02-23
Method And Apparatus For Thermal Modeling And Analysis Of Semiconductor Chip Designs App 20080243461 - Li; Peng ; et al.	2008-10-02
Method and apparatus for thermal modeling and analysis of semiconductor chip designs Grant 7,401,304 - Li , et al. July 15, 2	2008-07-15
Statistical optimization and design method for analog and digital circuits App 20060095888 - Li; Xin ; et al.	2006-05-04
Method and apparatus for thermal modeling and analysis of semiconductor chip designs App 20060031794 - Li; Peng ; et al.	2006-02-09
Programmable gate array based on configurable metal interconnect vias Grant 6,633,182 - Pileggi , et al. October 14, 2	2003-10-14
Programmable gate array based on configurable metal interconnect vias App 20030042930 - Pileggi, Larry ; et al.	2003-03-06

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