Pierson; Matthew D.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Pierson; Matthew D..The latest application filed is for "multicore bus architecture with wire reduction and physical congestion minimization via shared transaction channels".

Company Profile

4.36.36

Pierson; Matthew D. - Murphy TX
Pierson; Matthew D - Murphy TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Multicore Bus Architecture With Wire Reduction And Physical Congestion Minimization Via Shared Transaction Channels App 20220261373 - Thompson; David M. ; et al.	2022-08-18
Multicore bus architecture with wire reduction and physical congestion minimization via shared transaction channels Grant 11,321,268 - Thompson , et al. May 3, 2	2022-05-03
Slot/sub-slot Prefetch Architecture For Multiple Memory Requestors App 20210349827 - CHIRCA; Kai ; et al.	2021-11-11
Highly Integrated Scalable, Flexible Dsp Megamodule Architecture App 20210240634 - Anderson; Timothy D. ; et al.	2021-08-05
Slot/sub-slot prefetch architecture for multiple memory requestors Grant 11,074,190 - Chirca , et al. July 27, 2	2021-07-27
Highly integrated scalable, flexible DSP megamodule architecture Grant 11,036,648 - Anderson , et al. June 15, 2	2021-06-15
Multicore Bus Architecture With Non-blocking High Performance Transaction Credit System App 20210011872 - Thompson; David M. ; et al.	2021-01-14
Multicore bus architecture with non-blocking high performance transaction credit system Grant 10,795,844 - Thompson , et al. October 6, 2	2020-10-06
Slot/sub-slot Prefetch Architecture For Multiple Memory Requestors App 20200057723 - CHIRCA; Kai ; et al.	2020-02-20
Multicore Bus Architecture With Non-blocking High Performance Transaction Credit System App 20190354500 - Thompson; David M. ; et al.	2019-11-21
Slot/sub-slot prefetch architecture for multiple memory requestors Grant 10,394,718 - Chirca , et al. A	2019-08-27
Multicore bus architecture with non-blocking high performance transaction credit system Grant 10,311,007 - Thompson , et al.	2019-06-04
Highly Integrated Scalable, Flexible Dsp Megamodule Architecture App 20190146790 - Anderson; Timothy D. ; et al.	2019-05-16
Highly integrated scalable, flexible DSP megamodule architecture Grant 10,162,641 - Anderson , et al. Dec	2018-12-25
Secure Master And Secure Guest Endpoint Security Firewall App 20180357448 - Anderson; Timothy D. ; et al.	2018-12-13
Multicore Bus Architecture With Non-blocking High Performance Transaction Credit System App 20180293199 - THOMPSON; David M. ; et al.	2018-10-11
Slot/sub-slot Prefetch Architecture For Multiple Memory Requestors App 20180239710 - CHIRCA; Kai ; et al.	2018-08-23
Secure master and secure guest endpoint security firewall Grant 10,037,439 - Anderson , et al. July 31, 2	2018-07-31
Multicore bus architecture with non-blocking high performance transaction credit system Grant 9,904,645 - Thompson , et al. February 27, 2	2018-02-27
Slot/sub-slot prefetch architecture for multiple memory requestors Grant 9,898,415 - Chirca , et al. February 20, 2	2018-02-20
Highly Integrated Scalable, Flexible Dsp Megamodule Architecture App 20170153890 - Anderson; Timothy D. ; et al.	2017-06-01
Multicore, multibank, fully concurrent coherence controller Grant 9,652,404 - Pierson , et al. May 16, 2	2017-05-16
Highly integrated scalable, flexible DSP megamodule architecture Grant 9,606,803 - Anderson , et al. March 28, 2	2017-03-28
Multi-master cache coherent speculation aware memory controller with advanced arbitration, virtualization and EDC Grant 9,489,314 - Chirca , et al. November 8, 2	2016-11-08
Multi processor multi domain conversion bridge with out of order return buffering Grant 9,465,741 - Chirca , et al. October 11, 2	2016-10-11
Multi-processor, multi-domain, multi-protocol cache coherent speculation aware shared memory controller and interconnect Grant 9,465,767 - Chirca , et al. October 11, 2	2016-10-11
Flexible arbitration scheme for multi endpoint atomic accesses in multicore systems Grant 9,424,193 - Chirca , et al. August 23, 2	2016-08-23
Deadlock-avoiding coherent system on chip interconnect Grant 9,372,808 - Pierson , et al. June 21, 2	2016-06-21
Optimum cache access scheme for multi endpoint atomic access in a multicore system Grant 9,372,796 - Chirca , et al. June 21, 2	2016-06-21
Coherent cache system with optional acknowledgement for out-of-order coherence transaction completion Grant 9,372,799 - Wu , et al. June 21, 2	2016-06-21
Multicore, Multibank, Fully Concurrent Coherence Controller App 20160162407 - Pierson; Matthew D. ; et al.	2016-06-09
Multicore Bus Architecture With Non-Blocking High Performance Transaction Credit System App 20160124883 - Thompson; David M. ; et al.	2016-05-05
Multicore Bus Architecture With Wire Reduction and Physical Congestion Minimization Via Shared Transaction Channels App 20160124890 - Thompson; David M. ; et al.	2016-05-05
Distributed data return buffer for coherence system with speculative address support Grant 9,304,925 - Chirca , et al. April 5, 2	2016-04-05
Multi processor bridge with mixed Endian mode support Grant 9,304,954 - Wu , et al. April 5, 2	2016-04-05
Multicore, multibank, fully concurrent coherence controller Grant 9,298,665 - Pierson , et al. March 29, 2	2016-03-29
Flexible Arbitration Scheme For Multi Endpoint Atomic Accesses In Multicore Systems App 20160062887 - Chirca; Kai ; et al.	2016-03-03
Multi-Processor, Multi-Domain, Multi-Protocol Cache Coherent Speculation Aware Shared Memory Controller and Interconnect App 20160055096 - Chirca; Kai ; et al.	2016-02-25
Prefetcher with arbitrary downstream prefetch cancelation Grant 9,239,798 - Pierson , et al. January 19, 2	2016-01-19
Optional Acknowledgement For Out-of-order Coherence Transaction Completion App 20150370710 - Wu; Daniel B. ; et al.	2015-12-24
Flexible arbitration scheme for multi endpoint atomic accesses in multicore systems Grant 9,213,656 - Chirca , et al. December 15, 2	2015-12-15
Multi-processor, multi-domain, multi-protocol cache coherent speculation aware shared memory controller and interconnect Grant 9,208,120 - Chirca , et al. December 8, 2	2015-12-08
Coherent cache system with optional acknowledgement for out-of-order coherence transaction completion Grant 9,152,586 - Wu , et al. October 6, 2	2015-10-06
Coherence controller slot architecture allowing zero latency write commit Grant 9,129,071 - Pierson , et al. September 8, 2	2015-09-08
Hazard detection and elimination for coherent endpoint allowing out-of-order execution Grant 9,075,928 - Pierson , et al. July 7, 2	2015-07-07
Prefetch address hit prediction to reduce memory access latency Grant 9,009,414 - Anderson , et al. April 14, 2	2015-04-14
Prefetch stream filter with FIFO allocation and stream direction prediction Grant 8,977,819 - Chirca , et al. March 10, 2	2015-03-10
Highly Integrated Scalable, Flexible DSP Megamodule Architecture App 20150019840 - Anderson; Timothy D. ; et al.	2015-01-15
Double-buffered data storage to reduce prefetch generation stalls Grant 8,788,759 - Pierson , et al. July 22, 2	2014-07-22
Multicore, Multibank, Fully Concurrent Coherence Controller App 20140156951 - Pierson; Matthew D. ; et al.	2014-06-05
Multi-Processor, Multi-Domain, Multi-Protocol Cache Coherent Speculation Aware Shared Memory Controller and Interconnect App 20140149690 - Chirca; Kai ; et al.	2014-05-29
Flexible Arbitration Scheme For Multi Endpoint Atomic Accesses In Multicore Systems App 20140143486 - Chirca; Kai ; et al.	2014-05-22
Secure Master and Secure Guest Endpoint Security Firewall App 20140143849 - Anderson; Timothy D. ; et al.	2014-05-22
Multi Processor Multi Domain Conversion Bridge with Out of Order Return Buffering App 20140115210 - Chirca; Kai ; et al.	2014-04-24
Distributed Data Return Buffer For Coherence System With Speculative Address Support App 20140115273 - Chirca; Kai ; et al.	2014-04-24
Optional Acknowledgement For Out-of-order Coherence Transaction Completion App 20140115266 - Wu; Daniel B ; et al.	2014-04-24
Multi Processor Bridge With Mixed Endian Mode Support App 20140115270 - Wu; Daniel B. ; et al.	2014-04-24
Hazard Detection and Elimination for Coherent Endpoint Allowing Out-of-Order Execution App 20140115267 - Pierson; Matthew D ; et al.	2014-04-24
Coherence Controller Slot Architecture Allowing Zero Latency Write Commit App 20140115271 - Pierson; Matthew D. ; et al.	2014-04-24
Deadlock-Avoiding Coherent System On Chip Interconnect App 20140115272 - Pierson; Matthew D. ; et al.	2014-04-24
Optimum Cache Access Scheme For Multi Endpoint Atomic Access In A Multicore System App 20140115265 - Chirca; Kai ; et al.	2014-04-24
Multi-Master Cache Coherent Speculation Aware Memory Controller with Advanced Arbitration, Virtualization and EDC App 20140115279 - Chirca; Kai ; et al.	2014-04-24
Prefetch Address Hit Prediction To Reduce Memory Access Latency App 20120072672 - Anderson; Timothy D. ; et al.	2012-03-22
Slot/sub-slot Prefetch Architecture For Multiple Memory Requestors App 20120072668 - Chirca; Kai ; et al.	2012-03-22
Prefetcher With Arbitrary Downstream Prefetch Cancelation App 20120072702 - Pierson; Matthew D. ; et al.	2012-03-22
Prefetch Stream Filter With Fifo Allocation And Stream Direction Prediction App 20120072671 - Chirca; Kai ; et al.	2012-03-22
Double-buffered Data Storage To Reduce Prefetch Generation Stalls App 20120072674 - Pierson; Matthew D. ; et al.	2012-03-22

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