loadpatents
name:-0.011419057846069
name:-0.015017032623291
name:-0.00045490264892578
Piersimoni; Pietro Patent Filings

Piersimoni; Pietro

Patent Applications and Registrations

Patent applications and USPTO patent grants for Piersimoni; Pietro.The latest application filed is for "chip protection register unlocking".

Company Profile
0.11.7
  • Piersimoni; Pietro - Avezzano IT
  • Piersimoni; Pietro - Via Ruggero Grieco IT
  • Piersimoni, Pietro - Avezzano AQ
  • Piersimoni; Pietro - Fabriano IT
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Chip protection register unlocking
Grant 7,145,799 - Naso , et al. December 5, 2
2006-12-05
Write state machine architecture for flash memory internal instructions
Grant 7,136,307 - Piersimoni , et al. November 14, 2
2006-11-14
Multiple partition memory command user interface
Grant 7,028,135 - Piersimoni , et al. April 11, 2
2006-04-11
Write state machine architecture for flash memory internal instructions
Grant 7,027,331 - Piersimoni , et al. April 11, 2
2006-04-11
Chip protection register unlocking
App 20050237804 - Naso, Giovanni ;   et al.
2005-10-27
Chip protection register unlocking
Grant 6,947,323 - Naso , et al. September 20, 2
2005-09-20
Write state machine architecture for flash memory internal instructions
App 20050195655 - Piersimoni, Pietro ;   et al.
2005-09-08
Method for making a memory device with plural substrates each having a memory array, a read only memory, and a write state machine
Grant 6,879,522 - Piersimoni , et al. April 12, 2
2005-04-12
Write state machine architecture for flash memory internal instructions
App 20050005060 - Piersimoni, Pietro ;   et al.
2005-01-06
Chip protection register unlocking
App 20040151026 - Naso, Giovanni ;   et al.
2004-08-05
Write state machine architecture for flash memory internal instructions
App 20040047181 - Piersimoni, Pietro ;   et al.
2004-03-11
Write state machine architecture for flash memory internal instructions
Grant 6,618,291 - Piersimoni , et al. September 9, 2
2003-09-09
Multiple partition memory command user interface
App 20030062938 - Piersimoni, Pietro ;   et al.
2003-04-03
Write state machine architecture for flash memory internal instructions
App 20020114182 - Piersimoni, Pietro ;   et al.
2002-08-22
Low voltage, high current pump for flash memory
Grant 5,874,849 - Marotta , et al. February 23, 1
1999-02-23
Programmable and convertible non-volatile memory array
Grant 5,844,839 - Smayling , et al. December 1, 1
1998-12-01
Programmable and convertible non-volatile memory array
Grant 5,732,021 - Smayling , et al. March 24, 1
1998-03-24
Programmable memory verify "0" and verify "1" circuit and method
Grant 5,715,195 - Smayling , et al. February 3, 1
1998-02-03

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed