Pidaparthi; Subhash Srinivas

Patent Applications and Registrations

Patent applications and USPTO patent grants for Pidaparthi; Subhash Srinivas.The latest application filed is for "method and system for fabrication of a vertical fin-based field effect transistor".

Company Profile

1.3.11

Pidaparthi; Subhash Srinivas - Santa Clara CA
Pidaparthi; Subhash Srinivas - Apple Valley MN

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method And System For Fabrication Of A Vertical Fin-based Field Effect Transistor App 20220310843 - Drowley; Clifford ; et al.	2022-09-29
Method And System For Fabricating Fiducials Using Selective Area Growth App 20220293530 - Drowley; Clifford ; et al.	2022-09-15
Methods And Systems For Fabrication Of Vertical Fin-based Jfets App 20220254918 - Drowley; Clifford ; et al.	2022-08-11
Coupled Guard Rings For Edge Termination App 20220238643 - Drowley; Clifford ; et al.	2022-07-28
Method and system for fabrication of a vertical fin-based field effect transistor Grant 11,335,810 - Drowley , et al. May 17, 2	2022-05-17
Method and system for fabricating fiducials using selective area growth Grant 11,315,884 - Drowley , et al. April 26, 2	2022-04-26
Self-aligned Isolation For Self-aligned Contacts For Vertical Fets App 20220020743 - Drowley; Clifford ; et al.	2022-01-20
Method And System Of Junction Termination Extension In High Voltage Semiconductor Devices App 20220013626 - Pidaparthi; Subhash Srinivas ; et al.	2022-01-13
Method And System For Etch Depth Control In Iii-v Semiconductor Devices App 20210407815 - Chen; Wayne ; et al.	2021-12-30
Method And System For Regrown Source Contacts For Vertical Gallium Nitride Based Fets App 20210305404 - Drowley; Clifford ; et al.	2021-09-30
Regrowth Uniformity In Gan Vertical Devices App 20210210624 - Drowley; Clifford ; et al.	2021-07-08
Method And System For Jfet With Implant Isolation App 20210193846 - Drowley; Clifford ; et al.	2021-06-24
Method And System For Fabrication Of A Vertical Fin-based Field Effect Transistor App 20210028312 - Drowley; Clifford ; et al.	2021-01-28
Semiconductor topography and method for reducing gate induced drain leakage (GIDL) in MOS transistors Grant 8,154,088 - Khoueir , et al. April 10, 2	2012-04-10

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