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Supporting Multiple Memory Types In A Memory Slot
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Prefetch unit for use with a cache memory subsystem of a cache memory hierarchy
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Processor with dependence mechanism to predict whether a load is dependent on older store
Grant 7,415,597 - Filippo , et al. August 19, 2 | 2008-08-19 |
System and method to prevent in-flight instances of operations from disrupting operation replay within a data-speculative microprocessor
Grant 7,363,470 - Filippo , et al. April 22, 2 | 2008-04-22 |
Store-to-load forwarding buffer using indexed lookup
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Speculation pointers to identify data-speculative operations in microprocessor
Grant 7,266,673 - Filippo , et al. September 4, 2 | 2007-09-04 |
Cache memory subsystem including a fixed latency R/W pipeline
Grant 7,251,710 - Isaac , et al. July 31, 2 | 2007-07-31 |
System and method for modifying a load operation to include a register-to-register move operation in order to forward speculative load results to a dependent operation
Grant 7,222,226 - Lepak , et al. May 22, 2 | 2007-05-22 |
Load store unit with replay mechanism
Grant 7,165,167 - Filippo , et al. January 16, 2 | 2007-01-16 |
System and method for handling exceptional instructions in a trace cache based processor
Grant 7,133,969 - Alsup , et al. November 7, 2 | 2006-11-07 |
Data speculation based on stack-relative addressing patterns
Grant 7,089,400 - Pickett , et al. August 8, 2 | 2006-08-08 |
Retaining flag value associated with dead result data in freed rename physical register with an indicator to select set-aside register instead for renaming
Grant 7,043,626 - McMinn , et al. May 9, 2 | 2006-05-09 |
Processor with dependence mechanism to predict whether a load is dependent on older store
App 20060095734 - Filippo; Michael A. ; et al. | 2006-05-04 |
System and method for linking speculative results of load operations to register values
Grant 7,028,166 - Pickett April 11, 2 | 2006-04-11 |
Data speculation based on addressing patterns identifying dual-purpose register
Grant 7,024,537 - Pickett , et al. April 4, 2 | 2006-04-04 |
Integrated circuit with multiple microcode ROMs
Grant 6,957,319 - McMinn , et al. October 18, 2 | 2005-10-18 |
Efficient microcode entry access from sequentially addressed portion via non-sequentially addressed portion
Grant 6,957,322 - Pickett October 18, 2 | 2005-10-18 |
Apparatus and method for independently schedulable functional units with issue lock mechanism in a processor
Grant 6,944,744 - Ahmed , et al. September 13, 2 | 2005-09-13 |
System and method for handling exceptional instructions in a trace cache based processor
App 20050076180 - Alsup, Mitchell ; et al. | 2005-04-07 |
System and method of using speculative operand sources in order to speculatively bypass load-store operations
Grant 6,845,442 - Lepak , et al. January 18, 2 | 2005-01-18 |
Store-to-load forwarding buffer using indexed lookup
App 20050010744 - Filippo, Michael A. ; et al. | 2005-01-13 |
Load store unit with replay mechanism
App 20040255101 - Filippo, Michael A. ; et al. | 2004-12-16 |
Microprocessor employing a performance throttling mechanism for power management
Grant 6,826,704 - Pickett November 30, 2 | 2004-11-30 |
System and method to prevent in-flight instances of operations from disrupting operation replay within a data-speculative microprocessor
App 20040221139 - Filippo, Michael A. ; et al. | 2004-11-04 |
Speculation pointers to identify data-speculative operations in microprocessor
App 20040221140 - Filippo, Michael A. ; et al. | 2004-11-04 |
Apparatus and method for independently schedulable functional units with issue lock mechanism in a processor
App 20040181652 - Ahmed, Ashraf ; et al. | 2004-09-16 |
Partial linearly tagged cache memory system
App 20040181626 - Pickett, James K. | 2004-09-16 |
System and method for linking speculative results of load operations to register values
App 20040177236 - Pickett, James K. | 2004-09-09 |
Data speculation based on addressing patterns identifying dual-purpose register
App 20040143721 - Pickett, James K. ; et al. | 2004-07-22 |
Microcode patch device and method for patching microcode using match registers and patch routines
Grant 6,438,664 - McGrath , et al. A | 2002-08-20 |
Computer system including priorities for memory operations and allowing a higher priority memory operation to interrupt a lower priority memory operation
Grant 6,298,424 - Lewchuk , et al. October 2, 2 | 2001-10-02 |
Variable byte-length instructions using state of function bit of second byte of plurality of instructions bytes as indicative of whether first byte is a prefix byte
Grant 6,175,908 - Pickett January 16, 2 | 2001-01-16 |
Apparatus and method for tracing microprocessor instructions
Grant 6,106,573 - Mahalingaiah , et al. August 22, 2 | 2000-08-22 |
Stride-based data address prediction structure
Grant 6,079,006 - Pickett June 20, 2 | 2000-06-20 |
Instruction redefinition using model specific registers
Grant 6,076,156 - Pickett , et al. June 13, 2 | 2000-06-13 |
Computer system including priorities for memory operations and allowing a higher priority memory operation to interrupt a lower priority memory operation
Grant 6,058,461 - Lewchuk , et al. May 2, 2 | 2000-05-02 |
Superscalar microprocessor stack structure for judging validity of predicted subroutine return addresses
Grant 5,968,169 - Pickett October 19, 1 | 1999-10-19 |
Start of access instruction configured to indicate an access mode for fetching memory operands in a microprocessor
Grant 5,958,045 - Pickett September 28, 1 | 1999-09-28 |
Speculative register storage for storing speculative results corresponding to register updated by a plurality of concurrently recorded instruction
Grant 5,933,618 - Tran , et al. August 3, 1 | 1999-08-03 |
Context-dependent memory-mapped registers for transparent expansion of a register file
Grant 5,926,646 - Pickett , et al. July 20, 1 | 1999-07-20 |
Speculative register file for storing speculative register states and removing dependencies between instructions utilizing the register
Grant 5,892,936 - Tran , et al. April 6, 1 | 1999-04-06 |
Way prediction unit and a method for operating the same
Grant 5,848,433 - Tran , et al. December 8, 1 | 1998-12-08 |
Way prediction structure for predicting the way of a cache in which an access hits, thereby speeding cache access time
Grant 5,845,323 - Roberts , et al. December 1, 1 | 1998-12-01 |
Superscalar microprocessor load/store unit employing a unified buffer and separate pointers for load and store operations
Grant 5,832,297 - Ramagopal , et al. November 3, 1 | 1998-11-03 |
Superscalar microprocessor employing a way prediction unit to predict the way of an instruction fetch address and to concurrently provide a branch prediction address corresponding to the fetch address
Grant 5,764,946 - Tran , et al. June 9, 1 | 1998-06-09 |
Data memory unit and method for storing data into a lockable cache in one clock cycle by previewing the tag array
Grant 5,761,712 - Tran , et al. June 2, 1 | 1998-06-02 |
Superscalar microprocessor employing away prediction structure
Grant 5,752,069 - Roberts , et al. May 12, 1 | 1998-05-12 |
Interface circuit for interfacing a peripheral device with a microprocessor operating in either a synchronous or an asynchronous mode
Grant 5,339,395 - Pickett , et al. August 16, 1 | 1994-08-16 |
CMOS binary equals comparator with carry in and out
Grant 4,797,650 - Pickett January 10, 1 | 1989-01-10 |
CMOS binary threshold comparator
Grant 4,755,696 - Pickett July 5, 1 | 1988-07-05 |
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