Phillips; Christopher E.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Phillips; Christopher E..The latest application filed is for "fault tolerant integrated circuit architecture".

Company Profile

0.21.6

Phillips; Christopher E. - San Jose CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Fault tolerant integrated circuit architecture Grant 7,880,497 - Kelem , et al. February 1, 2	2011-02-01
Resilient integrated circuit architecture Grant 7,812,629 - Kelem , et al. October 12, 2	2010-10-12
Fault tolerant integrated circuit architecture Grant 7,705,624 - Kelem , et al. April 27, 2	2010-04-27
Fault Tolerant Integrated Circuit Architecture App 20100033207 - Kelem; Steven Hennick ; et al.	2010-02-11
Resilient Integrated Circuit Architecture App 20090134906 - Kelem; Steven Hennick ; et al.	2009-05-28
Fault Tolerant Integrated Circuit Architecture App 20090134907 - Kelem; Steven Hennick ; et al.	2009-05-28
Hierarchical storage architecture for reconfigurable logic configurations Grant 7,502,920 - Phillips , et al. March 10, 2	2009-03-10
Hierarchical storage architecture for reconfigurable logic configurations App 20050204122 - Phillips, Christopher E. ; et al.	2005-09-15
Method for compiling high level programming languages into embedded microprocessor with multiple reconfigurable logic Grant 6,708,325 - Cooke , et al. March 16, 2	2004-03-16
Efficient high performance data operation element for use in a reconfigurable logic environment App 20030088757 - Lindner, Joshua ; et al.	2003-05-08
Method For Compiling High Level Programming Languages App 20030014743 - COOKE, LAURENCE H. ; et al.	2003-01-16
Reconfigurable logic for table lookup Grant 6,389,579 - Phillips , et al. May 14, 2	2002-05-14
Control fabric unit including associated configuration memory and PSOP state machine adapted to provide configuration address to reconfigurable functional unit Grant 6,349,346 - Hanrahan , et al. February 19, 2	2002-02-19
Reconfigurable program sum of products generator Grant 6,311,200 - Hanrahan , et al. October 30, 2	2001-10-30
Behavioral silicon construct architecture and mapping Grant 6,298,472 - Phillips , et al. October 2, 2	2001-10-02
Configuration state memory for functional blocks on a reconfigurable chip Grant 6,288,566 - Hanrahan , et al. September 11, 2	2001-09-11
Integrated processor and programmable data path chip for reconfigurable computing Grant 6,282,627 - Wong , et al. August 28, 2	2001-08-28
Tagged prefetch and instruction decoder for variable length instruction set and method of operation Grant 6,237,074 - Phillips , et al. May 22, 2	2001-05-22
Integrated processor and programmable data path chip for reconfigurable computing Grant 5,970,254 - Cooke , et al. October 19, 1	1999-10-19
Method for compiling high level programming languages into an integrated processor with reconfigurable logic Grant 5,966,534 - Cooke , et al. October 12, 1	1999-10-12
Preprogramming testing in a field programmable gate array Grant 5,887,002 - Cooke , et al. March 23, 1	1999-03-23
Method and apparatus for fault testing a pipelined processor Grant 5,699,506 - Phillips , et al. December 16, 1	1997-12-16
Programmable input/output buffer circuit with test capability Grant 5,671,234 - Phillips , et al. September 23, 1	1997-09-23
Preprogramming testing in a field programmable gate array Grant 5,623,501 - Cooke , et al. April 22, 1	1997-04-22
Multiplexer with level shift capabilities Grant 5,534,798 - Phillips , et al. July 9, 1	1996-07-09
Preprogramming testing in a field programmable gate array Grant 5,347,519 - Cooke , et al. September 13, 1	1994-09-13
Programmable input/output buffer circuit with test capability Grant 5,221,865 - Phillips , et al. June 22, 1	1993-06-22

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