Philips Semiconductor, Inc.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Philips Semiconductor, Inc..The latest application filed is for "substrate noise isolation using selective buried diffusions".

Company Profile

0.11.10

Philips Semiconductor, Inc. -
Philips Semiconductor, Inc. - Tarrytown NY
Philips Semiconductor, Inc. - Sunnyvale CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Circuit arrangement and method for improving data management in a data communications circuit App 20020184413 - Wingen, Neal T.	2002-12-05
Reconfigurable digital filter having multiple filtering modes App 20020184275 - Dutta, Santanu ; et al.	2002-12-05
Substrate Noise Isolation Using Selective Buried Diffusions App 20020184558 - Sessions, D.C.	2002-12-05
Parallel data communication having multiple sync codes App 20020184549 - Ehmann, Gregory E.	2002-12-05
Automatic upgradeable UART circuit arrangement App 20020184411 - Wingen, Neal T. ; et al.	2002-12-05
Integrated circuit arrangement with feature control App 20020181641 - Wingen, Neal T.	2002-12-05
Power and frequency adjustable UART device App 20020184543 - Wingen, Neal T.	2002-12-05
Reset circuit and method therefor App 20020145454 - Jensen, Rune H.	2002-10-10
Dynamically configurable page table App 20020144072 - Anand, Vishal	2002-10-03
Pulse-width modulation with feedback to toggle module App 20020136290 - Houghton, William G.	2002-09-26
Semiconductor device with transparent link area for silicide applications and fabrication thereof Grant 6,326,675 - Scott , et al. December 4, 2	2001-12-04
Method and arrangement for hierarchical control of multiple test access port control modules Grant 6,311,302 - Cassetti , et al. October 30, 2	2001-10-30
Process to improve adhesion of PECVD cap layers in integrated circuits Grant 6,303,192 - Annapragada , et al. October 16, 2	2001-10-16
System and method for residue entrapment utilizing a polish and sacrificial fill for semiconductor fabrication Grant 6,287,972 - Ziger , et al. September 11, 2	2001-09-11
Method of forming dual gate oxide layers of varying thickness on a single substrate Grant 6,262,455 - Lutze , et al. July 17, 2	2001-07-17
Optimized metal etch process to enable the use of aluminum plugs Grant 6,255,226 - Zheng , et al. July 3, 2	2001-07-03
Semiconductor device with high-temperature-stable gate electrode for sub-micron applications and fabrication thereof Grant 6,208,004 - Cunningham March 27, 2	2001-03-27
Memory addressing system and method therefor Grant 6,202,140 - Rose , et al. March 13, 2	2001-03-13
Integrated circuit including patching circuitry to bypass portions of an internally flawed read only memory and a method therefore Grant 6,158,018 - Bernasconi , et al. December 5, 2	2000-12-05
Method and apparatus for reducing power consumption in digital electronic circuits Grant RE36,839 - Simmons , et al. August 29, 2	2000-08-29
High-speed modular exponentiator and multiplier Grant 6,085,210 - Buer July 4, 2	2000-07-04

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