| Patent | Date |
|---|
Latency reduction in touch sensitive systems
Grant 11,016,600 - Drumm , et al. May 25, 2 | 2021-05-25 |
Latency Reduction In Touch Sensitive Systems
App 20200012408 - Drumm; Owen ; et al. | 2020-01-09 |
Systems and methods for super speed packet transfer
Grant 8,825,925 - Singh , et al. September 2, 2 | 2014-09-02 |
Speed power efficient USB method
Grant 6,839,778 - Sartore , et al. January 4, 2 | 2005-01-04 |
Memory device with fixed length non interruptible burst
Grant 6,651,134 - Phelan November 18, 2 | 2003-11-18 |
Non-volatile static memory cell
Grant 6,556,487 - Ratnakumar , et al. April 29, 2 | 2003-04-29 |
Method, architecture and circuitry for independently configuring a multiple array memory device
Grant 6,499,089 - Phelan , et al. December 24, 2 | 2002-12-24 |
Direct bit line-bit line defect detection test mode for SRAM
Grant 6,388,927 - Churchill , et al. May 14, 2 | 2002-05-14 |
Random Access Memory Having A Read/write Address Bus And Process For Writing To And Reading From The Same
App 20020054535 - Arcoleo, Mathew R. ; et al. | 2002-05-09 |
Method and apparatus to prevent latch-up in CMOS devices
Grant 6,359,316 - Voss , et al. March 19, 2 | 2002-03-19 |
Random access memory having independent read port and write port and process for writing to and reading from the same
App 20010043506 - Arcoleo, Mathew R. ; et al. | 2001-11-22 |
Scan path circuitry including a programmable delay circuit
Grant 6,286,118 - Churchill , et al. September 4, 2 | 2001-09-04 |
Synchronous random access memory having a read/write address bus and process for writing to and reading from the same
Grant 6,262,937 - Arcoleo , et al. July 17, 2 | 2001-07-17 |
Scan path circuitry for programming a variable clock pulse width
Grant 6,115,836 - Churchill , et al. September 5, 2 | 2000-09-05 |
Circuit and method for implementing single-cycle read/write operation(s), and random access memory including the circuit and/or practicing the method
Grant 6,069,839 - Pancholy , et al. May 30, 2 | 2000-05-30 |
Test mode features for synchronous pipelined memories
Grant 6,006,347 - Churchill , et al. December 21, 1 | 1999-12-21 |
Scan path circuitry including an output register having a flow through mode
Grant 5,953,285 - Churchill , et al. September 14, 1 | 1999-09-14 |
Output driver transistor with multiple gate bodies
Grant 5,677,555 - Kalpakjian , et al. October 14, 1 | 1997-10-14 |
Differential latch sense amlifiers using feedback
Grant 5,504,443 - Gross , et al. April 2, 1 | 1996-04-02 |
Flexibilitiy for column redundancy in a divided array architecture
Grant 5,491,664 - Phelan February 13, 1 | 1996-02-13 |
Parallel TESTMODE
Grant 5,383,157 - Phelan January 17, 1 | 1995-01-17 |
Sense amplifier with limited output voltage swing and cross-coupled tail device feedback
Grant 5,347,183 - Phelan September 13, 1 | 1994-09-13 |
Integrated output buffer logic circuit with a memory circuit
Grant 5,087,840 - Davies , et al. February 11, 1 | 1992-02-11 |
Fast static random access memory with high storage capacity
Grant 5,040,152 - Voss , et al. August 13, 1 | 1991-08-13 |
Matrix memory with redundancy and minimizes delay
Grant 5,033,024 - O'Connell , et al. July 16, 1 | 1991-07-16 |
| 