| Patent | Date |
|---|
Transistors stacked on front-end p-type transistors
Grant 11,437,405 - Dewey , et al. September 6, 2 | 2022-09-06 |
Backside contacts for semiconductor devices
Grant 11,437,283 - Lilak , et al. September 6, 2 | 2022-09-06 |
Metallization structures for stacked device connectivity and their methods of fabrication
Grant 11,430,814 - Lilak , et al. August 30, 2 | 2022-08-30 |
Self-aligned local interconnects
Grant 11,424,160 - Lilak , et al. August 23, 2 | 2022-08-23 |
Leave-behind Protective Layer Having Secondary Purpose
App 20220246608 - LILAK; Aaron D. ; et al. | 2022-08-04 |
Isolation wall stressor structures to improve channel stress and their methods of fabrication
Grant 11,393,722 - Lilak , et al. July 19, 2 | 2022-07-19 |
Stacked transistors with Si PMOS and high mobility thin film transistor NMOS
Grant 11,393,818 - Dewey , et al. July 19, 2 | 2022-07-19 |
Stacked transistor architecture including nanowire or nanoribbon thin film transistors
Grant 11,380,684 - Dewey , et al. July 5, 2 | 2022-07-05 |
Pedestal fin structure for stacked transistor integration
Grant 11,374,004 - Lilak , et al. June 28, 2 | 2022-06-28 |
Integrated circuits with stacked transistors and methods of manufacturing the same using processes which fabricate lower gate structures following completion of portions of an upper transistor
Grant 11,374,024 - Lilak , et al. June 28, 2 | 2022-06-28 |
Stacked nanowire transistor structure with different channel geometries for stress
Grant 11,367,722 - Lilak , et al. June 21, 2 | 2022-06-21 |
Leave-behind protective layer having secondary purpose
Grant 11,348,916 - Lilak , et al. May 31, 2 | 2022-05-31 |
Stacked transistor structures with asymmetrical terminal interconnects
Grant 11,342,227 - Lilak , et al. May 24, 2 | 2022-05-24 |
Vertically Stacked Transistor Devices With Isolation Wall Structures Containing An Electrical Conductor
App 20220102246 - LILAK; Aaron D. ; et al. | 2022-03-31 |
Vertically stacked transistor devices with isolation wall structures containing an electrical conductor
Grant 11,257,738 - Lilak , et al. February 22, 2 | 2022-02-22 |
Stacked Forksheet Transistors
App 20210407999 - HUANG; Cheng-Ying ; et al. | 2021-12-30 |
Stacked Transistor Structures With Asymmetrical Terminal Interconnects
App 20210305098 - Lilak; Aaron ; et al. | 2021-09-30 |
Stacked Transistors With Si Pmos And High Mobility Thin Film Transistor Nmos
App 20210091080 - DEWEY; Gilbert ; et al. | 2021-03-25 |
Iii-v Source/drain In Top Nmos Transistors For Low Temperature Stacked Transistor Contacts
App 20210057413 - DEWEY; Gilbert ; et al. | 2021-02-25 |
Devices With Air Gapping Between Stacked Transistors And Process For Providing Such
App 20200411639 - MANNEBACH; Ehren ; et al. | 2020-12-31 |
Memory Devices With A Logic Region Between Memory Regions
App 20200411428 - Lilak; Aaron D. ; et al. | 2020-12-31 |
Sidewall Interconnect Metallization Structures For Integrated Circuit Devices
App 20200411433 - Lilak; Aaron ; et al. | 2020-12-31 |
Forming An Oxide Volume Within A Fin
App 20200411365 - HUANG; Cheng-Ying ; et al. | 2020-12-31 |
Stacked Source-drain-gate Connection And Process For Forming Such
App 20200411651 - MANNEBACH; Ehren ; et al. | 2020-12-31 |
Sideways Vias In Isolation Areas To Contact Interior Layers In Stacked Devices
App 20200411430 - MANNEBACH; Ehren ; et al. | 2020-12-31 |
Stacked Trigate Transistors With Dielectric Isolation And Process For Forming Such
App 20200411511 - RACHMADY; Willy ; et al. | 2020-12-31 |
Epitaxial Layer With Substantially Parallel Sides
App 20200411315 - HUANG; Cheng-Ying ; et al. | 2020-12-31 |
Metallization Structures For Stacked Device Connectivity And Their Methods Of Fabrication
App 20200395386 - Lilak; Aaron D. ; et al. | 2020-12-17 |
Isolation Wall Stressor Structures To Improve Channel Stress And Their Methods Of Fabrication
App 20200303257 - Lilak; Aaron D. ; et al. | 2020-09-24 |
Stacked Transistors Having Device Strata With Different Channel Widths
App 20200295003 - Dewey; Gilbert W. ; et al. | 2020-09-17 |
Stacked Transistors With Different Crystal Orientations In Different Device Strata
App 20200295127 - Mannebach; Ehren ; et al. | 2020-09-17 |
Stacked Transistors With Dielectric Between Source/drain Materials Of Different Strata
App 20200294969 - Rachmady; Willy ; et al. | 2020-09-17 |
Backside Contacts For Semiconductor Devices
App 20200294998 - LILAK; AARON D. ; et al. | 2020-09-17 |
Vertically Stacked Transistor Devices With Isolation Wall Structures Containing An Electrical Conductor
App 20200273779 - LILAK; Aaron D. ; et al. | 2020-08-27 |
Stacked Transistors With Dielectric Between Channels Of Different Device Strata
App 20200266218 - Lilak; Aaron D. ; et al. | 2020-08-20 |
Vertical Diode In Stacked Transistor Architecture
App 20200258881 - A1 | 2020-08-13 |
Self-aligned Local Interconnects
App 20200258778 - A1 | 2020-08-13 |
Integrated Circuits With Stacked Transistors And Methods Of Manufacturing The Same Using Processes Which Fabricate Lower Gate St
App 20200235134 - Lilak; Aaron D. ; et al. | 2020-07-23 |
Gate-all-around Integrated Circuit Structures Having Depopulated Channel Structures Using Multiple Bottom-up Oxidation Approache
App 20200219970 - Mannebach; Ehren ; et al. | 2020-07-09 |
Gate-all-around Integrated Circuit Structures Having Depopulated Channel Structures Using Bottom-up Oxidation Approach
App 20200219979 - RACHMADY; Willy ; et al. | 2020-07-09 |
Three Dimensional Integrated Circuits With Stacked Transistors
App 20200211905 - HUANG; Cheng-Ying ; et al. | 2020-07-02 |
Self-aligned Stacked Ge/si Cmos Transistor Structure
App 20200212038 - RACHMADY; Willy ; et al. | 2020-07-02 |
Transistors On Heterogeneous Bonding Layers
App 20200194570 - Jun; Kimin ; et al. | 2020-06-18 |
Stacked Transistor Architecture Including Nanowire Or Nanoribbon Thin Film Transistors
App 20200105751 - Dewey; Gilbert ; et al. | 2020-04-02 |
Vertically Stacked Cmos With Upfront M0 Interconnect
App 20200098921 - RACHMADY; Willy ; et al. | 2020-03-26 |
Stacked Nanowire Transistor Structure With Different Channel Geometries For Stress
App 20200098756 - Lilak; Aaron ; et al. | 2020-03-26 |
Interconnect Techniques For Electrically Connecting Source/drain Regions Of Stacked Transistors
App 20200006329 - LILAK; AARON D. ; et al. | 2020-01-02 |
Techniques For Forming Gate Structures For Transistors Arranged In A Stacked Configuration On A Single Fin Structure
App 20200006331 - LILAK; AARON D. ; et al. | 2020-01-02 |
Leave-behind Protective Layer Having Secondary Purpose
App 20200006330 - LILAK; AARON D. ; et al. | 2020-01-02 |
Pedestal Fin Structure For Stacked Transistor Integration
App 20200006340 - LILAK; AARON D. ; et al. | 2020-01-02 |
Transistors Stacked On Front-end P-type Transistors
App 20200006388 - DEWEY; Gilbert ; et al. | 2020-01-02 |
Stacked Transistors With Different Gate Lengths In Different Device Strata
App 20190196830 - Lilak; Aaron D. ; et al. | 2019-06-27 |
Parking event detection and location estimation
Grant 10,121,374 - Kazemi , et al. November 6, 2 | 2018-11-06 |
Parking Event Detection And Location Estimation
App 20170358208 - Kazemi; Pejman Lotfali ; et al. | 2017-12-14 |
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