Pham; Tim V.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Pham; Tim V..The latest application filed is for "die stack address bus having a programmable width".

Company Profile

0.20.23

Pham; Tim V. - Austin TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Defective die replacement in a die stack Grant 10,177,052 - Pelley , et al. J	2019-01-08
Die stack address bus having a programmable width Grant 10,002,653 - Pelley , et al. June 19, 2	2018-06-19
Thin low profile strip dual in-line memory module Grant 9,480,161 - Pelley , et al. October 25, 2	2016-10-25
Die Stack Address Bus Having A Programmable Width App 20160118095 - Pelley; Perry H. ; et al.	2016-04-28
Wirebond recess for stacked die Grant 9,318,451 - Pham , et al. April 19, 2	2016-04-19
Package encapsulant relief feature Grant 9,281,256 - Ding , et al. March 8, 2	2016-03-08
Matrix Lid Heatspreader for Flip Chip Package App 20160005682 - Leal; George R. ; et al.	2016-01-07
Matrix lid heatspreader for flip chip package Grant 9,159,643 - Leal , et al. October 13, 2	2015-10-13
Defective Die Replacement In A Die Stack App 20150287653 - Pelley; Perry H. ; et al.	2015-10-08
Thin Low Profile Strip Dual In-Line Memory Module App 20150208510 - Pelley; Perry H. ; et al.	2015-07-23
Edge coupling of semiconductor dies Grant 9,087,702 - Pham , et al. July 21, 2	2015-07-21
Heat conductive substrate for integrated circuit package Grant 9,070,657 - Pham , et al. June 30, 2	2015-06-30
Wirebond Recess For Stacked Die App 20150115474 - PHAM; TIM V. ; et al.	2015-04-30
Heat Conductive Substrate For Integrated Circuit Package App 20150097280 - Pham; Tim V. ; et al.	2015-04-09
Package Encapsulant Relief Feature App 20150084168 - DING; MIN ; et al.	2015-03-26
Recessed Semiconductor Die Stack App 20150069624 - Pham; Tim V. ; et al.	2015-03-12
Edge Coupling Of Semiconductor Dies App 20150061097 - Pham; Tim V. ; et al.	2015-03-05
Methods and structures for reducing stress on die assembly Grant 8,970,026 - Leal , et al. March 3, 2	2015-03-03
Using an integrated circuit die configuration for package height reduction Grant 8,957,510 - Pham , et al. February 17, 2	2015-02-17
Using An Integrated Circuit Die Configuration For Package Height Reduction App 20150008567 - PHAM; TIM V. ; et al.	2015-01-08
Fluid Cooled Semiconductor Die Package App 20140306336 - Foong; Chee Seng ; et al.	2014-10-16
Fluid cooled semiconductor die package Grant 8,860,212 - Foong , et al. October 14, 2	2014-10-14
Methods And Structures For Reducing Stress On Die Assembly App 20140225268 - LEAL; GEORGE R. ; et al.	2014-08-14
Matrix Lid Heatspreader for Flip Chip Package App 20140077352 - Leal; George R. ; et al.	2014-03-20
Dynamic pad size to reduce solder fatigue Grant 8,008,786 - Pham , et al. August 30, 2	2011-08-30
Dynamic Pad Size To Reduce Solder Fatigue App 20100264542 - Pham; Tim V. ; et al.	2010-10-21
Dynamic pad size to reduce solder fatigue Grant 7,772,104 - Pham , et al. August 10, 2	2010-08-10
Dynamic pad size to reduce solder fatigue App 20080185735 - Pham; Tim V. ; et al.	2008-08-07
Method for processing multiple semiconductor devices for test Grant 6,905,891 - Kovar , et al. June 14, 2	2005-06-14
Method for processing multiple semiconductor devices for test App 20030160315 - Kovar, Gary J. ; et al.	2003-08-28

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.