Pham; Ngan N.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Pham; Ngan N..The latest application filed is for "apparatus, system, and method for cache coherency elimination".

Company Profile

0.11.17

Pham; Ngan N. - Raliegh NC
Pham; Ngan N. - Raleigh NC US
Pham; Ngan N. - Research Triangle Park NC

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Dynamic initial cache line coherency state assignment in multi-processor systems Grant 8,838,909 - Colglazier , et al. September 16, 2	2014-09-16
Silent invalid state transition handling in an SMP environment Grant 8,812,793 - Kornegay , et al. August 19, 2	2014-08-19
Structure for silent invalid state transition handling in an SMP environment Grant 8,195,892 - Kornegay , et al. June 5, 2	2012-06-05
Structure for dynamic initial cache line coherency state assignment in multi-processor systems Grant 8,131,943 - Colglazier , et al. March 6, 2	2012-03-06
Structure for shared cache eviction Grant 8,065,487 - Kornegay , et al. November 22, 2	2011-11-22
Directory-based data transfer protocol for multiprocessor system Grant 7,925,838 - Dombrowski , et al. April 12, 2	2011-04-12
System and method for dynamically selecting the fetch path of data for improving processor performance Grant 7,865,669 - Kornegay , et al. January 4, 2	2011-01-04
Apparatus, System, And Method For Cache Coherency Elimination App 20100332763 - Kornegay; Marcus L. ; et al.	2010-12-30
Write-Back Coherency Data Cache for Resolving Read/Write Conflicts App 20100325367 - Kornegay; Marcus L. ; et al.	2010-12-23
Method and system for intelligent and dynamic cache replacement management based on efficient use of cache for individual processor core Grant 7,844,779 - Kornegay , et al. November 30, 2	2010-11-30
Method And System For Intelligent And Dynamic Cache Replacement Management Based On Efficient Use Of Cache For Individual Processor Core App 20090157970 - Kornegay; Marcus L. ; et al.	2009-06-18
System And Method For Dynamically Selecting The Fetch Path Of Data For Improving Processor Performance App 20090037664 - Kornegay; Marcus L. ; et al.	2009-02-05
Structure For Dynamic Initial Cache Line Coherency State Assignment In Multi-processor Systems App 20090019233 - COLGLAZIER; DANIEL J. ; et al.	2009-01-15
Dynamic Initial Cache Line Coherency State Assignment In Multi-processor Systems App 20090019230 - COLGLAZIER; Daniel J. ; et al.	2009-01-15
Directory-based Data Transfer Protocol For Multiprocessor System App 20080313427 - Dombrowski; Chris ; et al.	2008-12-18
Design Structure For Shared Cache Eviction App 20080235452 - KORNEGAY; MARCUS L. ; et al.	2008-09-25
Structure For Silent Invalid State Transition Handling In An Smp Environment App 20080215818 - Kornegay; Marcus L. ; et al.	2008-09-04
Structures, Systems And Arrangements For Cache Management App 20080209131 - Kornegay; Marcus L. ; et al.	2008-08-28
Structure For Administering An Access Conflict In A Computer Memory Cache App 20080201531 - Kornegay; Marcus L. ; et al.	2008-08-21
Directory-based data transfer protocol for multiprocessor system Grant 7,404,045 - Dombrowski , et al. July 22, 2	2008-07-22
Implementing A Hot Coherency State To A Cache Coherency Protocol In A Symmetric Multi-processor Environment App 20080140942 - Kornegay; Marcus L. ; et al.	2008-06-12
Systems and Arrangements for Cache Management App 20080120469 - Kornegay; Marcus L. ; et al.	2008-05-22
Method For Identifying, Tracking, And Storing Hot Cache Lines In An Smp Environment App 20080104323 - Colglazier; Daniel J. ; et al.	2008-05-01
Administering An Access Conflict In A Computer Memory Cache App 20080082755 - Kornegay; Marcus L. ; et al.	2008-04-03
Silent Invalid State Transition Handling In An Smp Environment App 20070294484 - Kornegay; Marcus L. ; et al.	2007-12-20
Directory-based data transfer protocol for multiprocessor system App 20070156970 - Dombrowski; Chris ; et al.	2007-07-05

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