Pflanz; Matthias

Patent Applications and Registrations

Patent applications and USPTO patent grants for Pflanz; Matthias.The latest application filed is for "stressing integrated circuits using a radiation source".

Company Profile

2.8.11

Pflanz; Matthias - Holzgerlingen DE
Pflanz; Matthias - Boeblingen DE
Pflanz; Matthias - Schoenaich DE
Pflanz; Matthias - Baden-Wurttemberg DE

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Stressing integrated circuits using a radiation source Grant 11,209,479 - Eckert , et al. December 28, 2	2021-12-28
Stressing Integrated Circuits Using A Radiation Source App 20210123969 - Eckert; Martin ; et al.	2021-04-29
Functional testing of high-speed serial links Grant 10,684,930 - Eckert , et al.	2020-06-16
Functional Testing Of High-speed Serial Links App 20190163596 - Eckert; Martin ; et al.	2019-05-30
Data processing in a multiple processor system to maintain multiple processor cache memory access coherency Grant 9,594,683 - Dittrich , et al. March 14, 2	2017-03-14
Data Processing In A Multiple Processor System App 20150154116 - Dittrich; Jens ; et al.	2015-06-04
Verification of logic circuit designs using dynamic clock gating Grant 8,302,043 - Habermann , et al. October 30, 2	2012-10-30
Controlling an unreliable data transfer in a data channel Grant 8,015,451 - Habermann , et al. September 6, 2	2011-09-06
Method, system, and computer program product for handling errors in a cache without processor core recovery Grant 7,987,384 - Jacobi , et al. July 26, 2	2011-07-26
Method and system for building binary decision diagrams optimally for nodes in a netlist graph using don't-caring Grant 7,949,968 - Jacobi , et al. May 24, 2	2011-05-24
Method, System, Computer Program Product, and Data Processing Program for Verification of Logic Circuit Designs Using Dynamic Clock Gating App 20110066988 - Habermann; Christian ; et al.	2011-03-17
Method and system for formal verification of an electronic circuit design Grant 7,890,903 - Weber , et al. February 15, 2	2011-02-15
Method And System For Formal Verification Of An Electronic Circuit Design App 20090300560 - Weber; Kai ; et al.	2009-12-03
Method, System, And Computer Program Product For Handling Errors In A Cache Without Processor Core Recovery App 20090204766 - Jacobi; Christian ; et al.	2009-08-13
Method and an Apparatus for Controlling an Unreliable Data Transfer in a Data Channel App 20090193308 - Habermann; Christian ; et al.	2009-07-30
Method and System for Building Binary Decision Diagrams Optimally for Nodes in a Netlist Graph Using Don't-Caring App 20080222590 - Jacobi; Christian ; et al.	2008-09-11
Method to Reduce Leakage Within a Sequential Network and Latch Circuit App 20070168792 - Barowski; Harry ; et al.	2007-07-19
Method and System for Performing Functional Formal Verification of Logic Circuits App 20070050740 - Jacobi; Christian ; et al.	2007-03-01
Method and Processor for Performing a Floating-Point Instruction Within a Processor App 20070038693 - Jacobi; Christian ; et al.	2007-02-15

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.