Pey; Kin Leong

Patent Applications and Registrations

Patent applications and USPTO patent grants for Pey; Kin Leong.The latest application filed is for "slot designs in wide metal lines".

Company Profile

0.38.19

Pey; Kin Leong - Singapore SG

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Control gate dummy for word line uniformity and method for producing the same Grant 10,381,360 - Luo , et al. A	2019-08-13
Slot Designs In Wide Metal Lines App 20160233157 - LIM; Yeow Kheng ; et al.	2016-08-11
Slot designs in wide metal lines Grant 9,318,378 - Lim , et al. April 19, 2	2016-04-19
RRAM cell with bottom electrode(s) positioned in a semiconductor substrate Grant 9,024,286 - Liu , et al. May 5, 2	2015-05-05
Low OHMIC contacts Grant 8,922,003 - Tan , et al. December 30, 2	2014-12-30
Rram Cell With Bottom Electrode(s) Positioned In A Semiconductor Substrate App 20140077148 - Liu; Wenhu ; et al.	2014-03-20
Low Ohmic Contacts App 20130187264 - TAN; Dexter Xueming ; et al.	2013-07-25
Method for fabricating nano devices Grant 8,338,280 - Tan , et al. December 25, 2	2012-12-25
Fabrication of RRAM Cell Using CMOS Compatible Processes App 20120241710 - Liu; Wenhu ; et al.	2012-09-27
Method for fabricating semiconductor devices with shallow diffusion regions Grant 8,101,487 - Tan , et al. January 24, 2	2012-01-24
Method For Fabricating Nano Devices App 20120009749 - TAN; Dexter ; et al.	2012-01-12
Formation of strained Si channel and Si.sub.1-xGe.sub.x source/drain structures using laser annealing Grant 7,892,905 - Ong , et al. February 22, 2	2011-02-22
Method for forming a shallow junction region using defect engineering and laser annealing Grant 7,888,224 - Ong , et al. February 15, 2	2011-02-15
Method For Forming A Shallow Junction Region Using Defect Engineering And Laser Annealing App 20100124809 - Ong; Kuang Kian ; et al.	2010-05-20
Method For Fabricating Semiconductor Devices With Shallow Diffusion Regions App 20090286373 - TAN; Dexter Xueming ; et al.	2009-11-19
Integrated circuit system using dual damascene process Grant 7,253,097 - Lim , et al. August 7, 2	2007-08-07
Formation of strained Si channel and Si1-xGex source/drain structures using laser annealing App 20070032026 - Ong; Kuang Kian ; et al.	2007-02-08
Integrated Circuit System Using Dual Damascene Process App 20070001303 - Lim; Yeow Kheng ; et al.	2007-01-04
Method and apparatus for performing nickel salicidation Grant 7,030,451 - Lee , et al. April 18, 2	2006-04-18
Dual metal gate process: metals and their silicides Grant 7,005,716 - Lin , et al. February 28, 2	2006-02-28
Slot designs in wide metal lines App 20060040491 - Lim; Yeow Kheng ; et al.	2006-02-23
Method and apparatus for performing nickel salicidation App 20050156269 - Lee, Pooi See ; et al.	2005-07-21
Methods to form dual metal gates by incorporating metals and their conductive oxides Grant 6,891,233 - Lin , et al. May 10, 2	2005-05-10
Method and apparatus for performing nickel salicidation Grant 6,890,854 - Lee , et al. May 10, 2	2005-05-10
Methods to form dual metal gates by incorporating metals and their conductive oxides Grant 6,835,989 - Lin , et al. December 28, 2	2004-12-28
Dual metal gate process: metals and their silicides App 20040217429 - Lin, Wenhe ; et al.	2004-11-04
Methods to form dual metal gates by incorporating metals and their conductive oxides App 20040132239 - Lin, Wenhe ; et al.	2004-07-08
Methods to form dual metal gates by incorporating metals and their conductive oxides App 20040132296 - Lin, Wenhe ; et al.	2004-07-08
Dual metal gate process: metals and their silicides Grant 6,750,519 - Lin , et al. June 15, 2	2004-06-15
Dual metal gate process: metals and their silicides App 20040065930 - Lin, Wenhe ; et al.	2004-04-08
Methods to form dual metal gates by incorporating metals and their conductive oxides Grant 6,677,652 - Lin , et al. January 13, 2	2004-01-13
Formation of silicided shallow junctions using implant through metal technology and laser annealing process Grant 6,624,489 - Chong , et al. September 23, 2	2003-09-23
Methods to form dual metal gates by incorporating metals and their conductive oxides App 20030075766 - Lin, Wenhe ; et al.	2003-04-24
Method to reduce variation in LDD series resistance Grant 6,534,388 - Lin , et al. March 18, 2	2003-03-18
Salicide method for producing a semiconductor device using silicon/amorphous silicon/metal structure Grant 6,534,390 - Chong , et al. March 18, 2	2003-03-18
Dual metal gate process: metals and their silicides Grant 6,475,908 - Lin , et al. November 5, 2	2002-11-05
Methods to form dual metal gates by incorporating metals and their conductive oxides Grant 6,458,695 - Lin , et al. October 1, 2	2002-10-01
Formation of silicided shallow junctions using implant through metal technology and laser annealing process App 20020098689 - Chong, Yung Fu ; et al.	2002-07-25
Method for fabricating void-free epitaxial-CoSi2 with ultra-shallow junctions Grant 6,410,429 - Ho , et al. June 25, 2	2002-06-25
Method and apparatus for performing nickel salicidation App 20020064918 - Lee, Pooi See ; et al.	2002-05-30
Activating source and drain junctions and extensions using a single laser anneal Grant 6,391,731 - Chong , et al. May 21, 2	2002-05-21
Method to reduce polysilicon depletion in MOS transistors Grant 6,387,784 - Chong , et al. May 14, 2	2002-05-14
Formation of silicided ultra-shallow junctions using implant through metal technology and laser annealing process Grant 6,365,446 - Chong , et al. April 2, 2	2002-04-02
Methods for effective nickel silicide formation Grant 6,339,021 - Tan , et al. January 15, 2	2002-01-15
Method to form MOS transistors with shallow junctions using laser annealing Grant 6,335,253 - Chong , et al. January 1, 2	2002-01-01
Method to reduce compressive stress in the silicon substrate during silicidation Grant 6,284,610 - Cha , et al. September 4, 2	2001-09-04
Optimized Co/Ti-salicide scheme for shallow junction deep sub-micron device fabrication Grant 6,271,133 - Lim , et al. August 7, 2	2001-08-07
Method to fabricate a double-polysilicon gate structure for a sub-quarter micron self-aligned-titanium silicide process Grant 6,180,501 - Pey , et al. January 30, 2	2001-01-30
Salicide formation on narrow poly lines by pulling back of spacer Grant 6,153,485 - Pey , et al. November 28, 2	2000-11-28
Selective CVD TiSi.sub.2 deposition with TiSi.sub.2 liner Grant 6,110,811 - Pey August 29, 2	2000-08-29
Ultra-low sheet resistance metal/poly-si gate for deep sub-micron CMOS application Grant 6,093,628 - Lim , et al. July 25, 2	2000-07-25
Silicon nitride--TEOS oxide, salicide blocking layer for deep sub-micron devices Grant 6,025,267 - Pey , et al. February 15, 2	2000-02-15
Cmos gate architecture for integration of salicide process in sub 0.1 . .muM devices Grant 6,010,954 - Ho , et al. January 4, 2	2000-01-04
Method of making self-aligned silicide narrow gate electrodes for field effect transistors having low sheet resistance Grant 5,731,239 - Wong , et al. March 24, 1	1998-03-24

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.